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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 徐慰中(Wei-Chung Hsu) | |
| dc.contributor.author | Shih-Kai Lin | en |
| dc.contributor.author | 林士凱 | zh_TW |
| dc.date.accessioned | 2021-06-17T03:14:53Z | - |
| dc.date.available | 2019-07-19 | |
| dc.date.copyright | 2018-07-19 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-07-09 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/69406 | - |
| dc.description.abstract | 事務性同步擴展是英特爾第四代處理器上所實作的事務內存，提供兩種編程接口，分別為：硬件鎖省略及受限事務內存 。前者較容易做編程，且擁有向下相容性、可以在不支援事務性同步擴展的硬體上執行；後者則是提供較大的彈性及擴充性。在以前的研究中顯示，由受限事務內存所保護的臨界區段配合良好設計的重試機制通常可以擁有優於硬件所省略的執行效能。簡而言之，雖然易於使用的緣故，可能較多的平行應用是使用硬件鎖省略，但改用受限事務內存可能帶來更佳的效能體驗。
我們提出一個機於QEMU上實作的框架，可以在運行中將硬件鎖省略的指令轉換成受限事務內存的程式碼片段，並能夠動態地進行績效調整。與原本的硬件鎖省略執行結果相比，我們機於動態二進制轉換上的實作可以在四執行緒的狀況下獲得平均1.15倍的效能提升，以及在八執行緒的狀況下獲得平均1.56倍的效能提升。因為受限事務內存所擁有的擴展性，當執行緒數量越多時，效能提升的現象會更加顯著。 | zh_TW |
| dc.description.abstract | Transactional Synchronization Extensions (TSX) support hardware Transactional Memory (TM) on Intel 4th generation Core processors. Two programming interfaces, Hardware Lock Elision (HLE) and Restricted Transactional Memory (RTM), are provided to support software development using TSX. HLE is easy to use and maintains backward compatible with processors without TSX support while RTM is more flexible and scalable. Previous researches have shown that critical sections protected by RTM with a well-designed retry mechanism as its fallback code path can often achieve better performance than HLE. More parallel programs may be programmed in HLE, however, using RTM may obtain greater performance.
To embrace both productivity and high performance of parallel program with TSX, we present a framework built on QEMU that can dynamically transform HLE instructions in an application binary to fragments of RTM codes with adaptive tuning on the fly. Compared to HLE execution, our prototype achieves 1.15x speedup with 4 threads and 1.56x speedup with 8 threads on average. Due to the scalability of RTM, the speedup will be more significant as the number of threads increases. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T03:14:53Z (GMT). No. of bitstreams: 1 ntu-107-R05922043-1.pdf: 578561 bytes, checksum: 8bde84a711a28773005d8d7516cc74a5 (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 口試委員會審定書 . . . . . . . . . . . . . . . . . . . . . . . . . iii
誌謝 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v 摘要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Intel Transactional Memory System . . . . . . . . . . . . . . 5 2.1.1 Hardware Lock Elision . . . . . . . . . . . . . . . . . . . 6 2.1.2 Restricted Transactional Memory . . . . . . . . . . . . . . 6 2.1.3 Retry Mechanism with RTM . . . . . . . . . . . . . . . . . . 7 2.2 Dynamic Binary Translation . . . . . . . . . . . . . . . . . . 7 3 HLE-to-RTM Transformation . . . . . . . . . . . . . . . . . . . 9 3.1 Transformation Method . . . . . . . . . . . . . . . . . . . . 9 3.2 Dynamic Tuning of Restricted Transactional Memory . . . . . . 12 4 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Results of HLE-to-RTM Transformation . . . . . . . . . . . . . 16 4.3 Native Performance Results with RTM . . . . . . . . . . . . . 19 5 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 | |
| dc.language.iso | en | |
| dc.subject | 硬體事務內存 | zh_TW |
| dc.subject | 事務性同步擴展 | zh_TW |
| dc.subject | 動態二進制轉換 | zh_TW |
| dc.subject | 重試機制 | zh_TW |
| dc.subject | 動態績效調整 | zh_TW |
| dc.subject | Hardware Transactional Memory | en |
| dc.subject | Dynamic Binary Translation | en |
| dc.subject | Retry Mechanism | en |
| dc.subject | Dynamic Tuning | en |
| dc.subject | Intel Transactional Synchronization Extensions | en |
| dc.title | 使用受限事務內存的應用程式之動態績效調整 | zh_TW |
| dc.title | Dynamic Tuning of Applications using Restricted Transactional Memory | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張鈞法(Chun-Fa Chang),吳真貞(Jan-Jan Wu),洪鼎詠(Ding-Yong Hong) | |
| dc.subject.keyword | 硬體事務內存,事務性同步擴展,動態績效調整,重試機制,動態二進制轉換, | zh_TW |
| dc.subject.keyword | Hardware Transactional Memory,Intel Transactional Synchronization Extensions,Dynamic Tuning,Retry Mechanism,Dynamic Binary Translation, | en |
| dc.relation.page | 28 | |
| dc.identifier.doi | 10.6342/NTU201800901 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-07-10 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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