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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳奕君(I-Chun Cheng) | |
dc.contributor.author | Chia-Hsun Tsai | en |
dc.contributor.author | 蔡佳勳 | zh_TW |
dc.date.accessioned | 2021-06-17T02:24:33Z | - |
dc.date.available | 2020-09-04 | |
dc.date.copyright | 2017-09-04 | |
dc.date.issued | 2017 | |
dc.date.submitted | 2017-08-18 | |
dc.identifier.citation | 參考文獻 [1] L. J. Edgar, 'Device for Controlling Electric Current,' ed: Google Patents, 1933. [2] P. K. Weimer, 'The TFT a New Thin-Film Transistor,' Proceedings of the IRE, vol. 50, pp. 1462-1469, 1962. [3] H. Klasens and H. Koelmans, 'A Tin Oxide Field-Effect Transistor,' Solid-State Electronics, vol. 7, pp. 701-702, 1964. [4] T. Brody, J. A. Asars, and G. D. Dixon, 'A 6× 6 Inch 20 Lines-Per-Inch Liquid-Crystal Display Panel,' IEEE Transactions on Electron Devices, vol. 20, pp. 995-1001, 1973. [5] P. Le Comber, W. Spear, and A. Ghaith, 'Amorphous-Silicon Field-Effect Device and Possible Application,' Electronics Letters, vol. 15, pp. 179-181, 1979. [6] A. Snell, W. Spear, P. Le Comber, and K. Mackenzie, 'Application of Amorphous Silicon Field Effect Transistors in Integrated Circuits,' Applied Physics A, vol. 26, pp. 83-86, 1981. [7] L. Petti, N. Münzenrieder, C. Vogt, H. Faber, L. Büthe, G. Cantarella, et al., 'Metal Oxide Semiconductor Thin-Film Transistors for Flexible Electronics,' Applied Physics Reviews, vol. 3, p. 021303, 2016. [8] E. Fortunato, P. Barquinha, and R. Martins, 'Oxide Semiconductor Thin‐Film Transistors: A Review of Recent Advances,' Advanced Materials, vol. 24, pp. 2945-2986, 2012. [9] A. C. Tickle, 'Thin-Film Transistors: A New Approach to Microelectronics,' 1969. [10] J. S. Park, W.-J. Maeng, H.-S. Kim, and J.-S. Park, 'Review of Recent Developments in Amorphous Oxide Semiconductor Thin-Film Transistor Devices,' Thin Solid Films, vol. 520, pp. 1679-1693, 2012. [11] A. Suresh, 'Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors, Non-Volatile Memory and Circuits for Transparent Electronics,' 2010. [12] G. Liu, A. Liu, H. Zhu, B. Shin, E. Fortunato, R. Martins, et al., 'Low‐Temperature, Nontoxic Water‐Induced Metal‐Oxide Thin Films and Their Application in Thin‐Film Transistors,' Advanced Functional Materials, vol. 25, pp. 2564-2572, 2015. [13] Y. Ogo, H. Hiramatsu, K. Nomura, H. Yanagi, T. Kamiya, M. Hirano, et al., 'P-channel Thin-Film Transistor Using P-type Oxide Semiconductor, SnO,' Applied Physics Letters, vol. 93, p. 032113, 2008. [14] Y. Ogo, H. Hiramatsu, K. Nomura, H. Yanagi, T. Kamiya, M. Kimura, et al., 'Tin Monoxide as an S‐Orbital‐Based P‐type Oxide Semiconductor: Electronic Structures and TFT Application,' Physica Status Solidi (a), vol. 206, pp. 2187-2191, 2009. [15] Z. Wang, P. K. Nayak, J. A. Caraveo‐Frescas, and H. N. Alshareef, 'Recent Developments in P‐type Oxide Semiconductor Materials and Devices,' Advanced Materials, vol. 28, pp. 3831-3892, 2016. [16] Z. Yao, B. He, L. Zhang, C. Zhuang, T. Ng, S. Liu, et al., 'Energy Band Engineering and Controlled P‐type Conductivity of CuAlO2 Thin Films by Nonisovalent Cu‐O Alloying,' Applied Physics Letters, vol. 100, p. 062102, 2012. [17] S.-Y. Sung, S.-Y. Kim, K.-M. Jo, J.-H. Lee, J.-J. Kim, S.-G. Kim, et al., 'Fabrication of P-channel Thin-Film Transistors Using CuO Active Layers Deposited at Low Temperature,' Applied Physics Letters, vol. 97, p. 222109, 2010. [18] X. Zou, G. Fang, L. Yuan, M. Li, W. Guan, and X. Zhao, 'Top-Gate Low-Threshold Voltage p-Cu2O Thin-Film Transistor Grown on SiO2/Si Substrate Using a High-κ HfON Gate Dielectric,' IEEE Electron Device Letters, vol. 31, p. 827, 2010. [19] J. Jiang, X. Wang, Q. Zhang, J. Li, and X. Zhang, 'Thermal Oxidation of Ni Films for P-type Thin-Film Transistors,' Physical Chemistry Chemical Physics, vol. 15, pp. 6875-6878, 2013. [20] A. Liu, G. Liu, H. Zhu, B. Shin, E. Fortunato, R. Martins, et al., 'Hole Mobility Modulation of Solution-Processed Nickel Oxide Thin-Film Transistor Based on High-k Dielectric,' Applied Physics Letters, vol. 108, p. 233506, 2016. [21] B. Zhu, Y. Yang, W. Hu, J. Wu, Z. Gan, J. Liu, et al., 'Transparent Conductive F-doped SnO2 Films Prepared by RF Reactive Magnetron Sputtering at Low Substrate Temperature,' Applied Physics A, vol. 123, p. 217, 2017. [22] H. J. Sharma, M. A. Salorkar, and S. B. Kondawar, 'H2 and CO Gas Sensor from SnO2/Polyaniline Composite Nanofibers Fabricated by Electrospinning,' in Advanced Materials Proceedings, 2017, pp. 61-66. [23] Z. Zhu, Y. Bai, X. Liu, C. C. Chueh, S. Yang, and A. K. Y. Jen, 'Enhanced Efficiency and Stability of Inverted Perovskite Solar Cells Using Highly Crystalline SnO2 Nanocrystals as the Robust Electron‐Transporting Layer,' Advanced Materials, vol. 28, pp. 6478-6484, 2016. [24] F. Zhang, J. Zhu, D. Zhang, U. Schwingenschlögl, and H. N. Alshareef, 'Two-Dimensional SnO Anodes with a Tunable Number of Atomic Layers for Sodium Ion Batteries,' Nano Letters, vol. 17, pp. 1302-1311, 2017. [25] R. Sivaramasubramaniam, M. Muhamad, and S. Radhakrishna, 'Optical Properties of Annealed Tin (II) Oxide in Different Ambients,' Physica Status Solidi (a), vol. 136, pp. 215-222, 1993. [26] A. Togo, F. Oba, I. Tanaka, and K. Tatsumi, 'First-Principles Calculations of Native Defects in Tin Monoxide,' Physical Review B, vol. 74, p. 195128, 2006. [27] J. P. Allen, D. O. Scanlon, S. C. Parker, and G. W. Watson, 'Tin Monoxide: Structural Prediction from First Principles Calculations with Van Der Waals Corrections,' The Journal of Physical Chemistry C, vol. 115, pp. 19916-19924, 2011. [28] J. Varley, A. Schleife, A. Janotti, and C. Van de Walle, 'Ambipolar Doping in SnO,' Applied Physics Letters, vol. 103, p. 082118, 2013. [29] H. Hosono, Y. Ogo, H. Yanagi, and T. Kamiya, 'Bipolar Conduction in SnO Thin Films,' Electrochemical and Solid-State Letters, vol. 14, pp. H13-H16, 2011. [30] E. Fortunato, R. Barros, P. Barquinha, V. Figueiredo, S.-H. K. Park, C.-S. Hwang, et al., 'Transparent P-type SnOx Thin Film Transistors Produced by Reactive RF Magnetron Sputtering Followed by Low Temperature Annealing,' Applied Physics Letters, vol. 97, p. 052105, 2010. [31] S.-S. Lin, Y.-S. Tsai, and K.-R. Bai, 'Structural and Physical Properties of Tin Oxide Thin Films for Optoelectronic Applications,' Applied Surface Science, vol. 380, pp. 203-209, 2016. [32] S. Cahen, N. David, J. Fiorani, A. Maıtre, and M. Vilasi, 'Thermodynamic Modelling of the O–Sn System,' Thermochimica Acta, vol. 403, pp. 275-285, 2003. [33] H. Luo, L. Y. Liang, H. T. Cao, Z. M. Liu, and F. Zhuge, 'Structural, Chemical, Optical, and Electrical Evolution of SnOx Films Deposited by Reactive RF Magnetron Sputtering,' ACS Applied Materials Interfaces, vol. 4, pp. 5673-5677, 2012. [34] J. A. Caraveo-Frescas, P. K. Nayak, H. A. Al-Jawhari, D. B. Granato, U. Schwingenschlögl, and H. N. Alshareef, 'Record Mobility in Transparent P-type Tin Monoxide Films and Devices by Phase Engineering,' ACS Nano, vol. 7, pp. 5160-5167, 2013. [35] H. Yabuta, N. Kaji, R. Hayashi, H. Kumomi, K. Nomura, T. Kamiya, et al., 'Sputtering Formation of P-type SnO Thin-Film Transistors on Glass toward Oxide Complimentary Circuits,' Applied Physics Letters, vol. 97, p. 072111, 2010. [36] J. Caraveo-Frescas and H. N. Alshareef, 'Transparent P-type SnO Nanowires with Unprecedented Hole Mobility among Oxide Semiconductors,' Applied Physics Letters, vol. 103, p. 222103, 2013. [37] I.-T. Cho, U. Myeonghun, S.-H. Song, J.-H. Lee, and H.-I. Kwon, 'Effects of Air-Annealing on the Electrical Properties of P-type Tin Monoxide Thin-Film Transistors,' Semiconductor Science and Technology, vol. 29, p. 045001, 2014. [38] C.-W. Zhong, H.-C. Lin, K.-C. Liu, and T.-Y. Huang, 'Impact of Thermal Oxygen Annealing on the Properties of Tin Oxide Films and Characteristics of P-type Thin-Film Transistors,' Japanese Journal of Applied Physics, vol. 55, p. 016501, 2015. [39] H.-I. Kwon, 'High Performance P-type SnO thin-film Transistor with SiOx Gate Insulator Deposited by Low-Temperature PECVD Method,' Journal of Semiconductor Technology and Science, vol. 14, p. 667, 2014. [40] Y. Li, Q. Xin, L. Du, Y. Qu, H. Li, X. Kong, et al., 'Extremely Sensitive Dependence of SnOx Film Properties on Sputtering Power,' Scientific Reports, vol. 6, 2016. [41] A. H.-T. Nguyen, M.-C. Nguyen, J. Choi, S. Han, J. Kim, and R. Choi, 'Electrical Performance Enhancement of P-type Tin Oxide Channel Thin Film Transistor Using Aluminum Doping,' Thin Solid Films, 2017. [42] P.-C. Chen, Y.-C. Chiu, G.-L. Liou, Z.-W. Zheng, C.-H. Cheng, and Y.-H. Wu, 'Performance Enhancements in P-type Al-Doped Tin-Oxide Thin Film Transistors by Using Fluorine Plasma Treatment,' IEEE Electron Device Letters, vol. 38, pp. 210-212, 2017. [43] K. Nomura, T. Kamiya, and H. Hosono, 'Ambipolar Oxide Thin‐Film Transistor,' Advanced Materials, vol. 23, pp. 3431-3434, 2011. [44] R. Martins, V. Figueiredo, R. Barros, P. Barquinha, G. Gonçalves, L. Pereira, et al., 'P-type Oxide-Based Thin Film Transistors Produced at Low Temperatures,' in SPIE OPTO, 2012, pp. 826315-826315-15. [45] L. Yan Liang, H. Tao Cao, X. Bo Chen, Z. Min Liu, F. Zhuge, H. Luo, et al., 'Ambipolar Inverters Using SnO Thin-Film Transistors with Balanced Electron and Hole Mobilities,' Applied Physics Letters, vol. 100, p. 263502, 2012. [46] P.-C. Hsu, W.-C. Chen, Y.-T. Tsai, Y.-C. Kung, C.-H. Chang, C.-J. Hsu, et al., 'Fabrication of P-type SnO Thin-Film Transistors by Sputtering with Practical Metal Electrodes,' Japanese Journal of Applied Physics, vol. 52, p. 05DC07, 2013. [47] Y.-J. Han, Y.-J. Choi, I.-T. Cho, S. H. Jin, J.-H. Lee, and H.-I. Kwon, 'Improvement of Long-Term Durability and Bias Stress Stability in P-type SnO Thin-Film Transistors Using a SU-8 Passivation Layer,' IEEE Electron Device Letters, vol. 35, pp. 1260-1262, 2014. [48] H.-N. Lee, B.-J. Song, and J. C. Park, 'Fabrication of P-channel Amorphous Tin Oxide Thin-Film Transistors Using a Thermal Evaporation Process,' Journal of Display Technology, vol. 10, pp. 288-292, 2014. [49] Y.-J. Han, Y.-J. Choi, C.-Y. Jeong, D. Lee, S.-H. Song, and H.-I. Kwon, 'Environment-Dependent Bias Stress Stability of P-type SnO Thin-Film Transistors,' IEEE Electron Device Letters, vol. 36, pp. 466-468, 2015. [50] Z. Wang, H. A. Al-Jawhari, P. K. Nayak, J. Caraveo-Frescas, N. Wei, M. N. Hedhili, et al., 'Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer,' Scientific Reports, vol. 5, 2015. [51] C. Zhong, H. Tsai, H. Lin, K. Liu, and T. Huang, 'Stability of High Performance P-type SnO TFTs,' in Physical and Failure Analysis of Integrated Circuits (IPFA), 2015, pp. 84-87. [52] C.-W. Zhong, H.-C. Lin, J.-R. Tsai, K.-C. Liu, and T.-Y. Huang, 'Impact of Gate Dielectrics and Oxygen Annealing on Tin-Oxide Thin-Film Transistors,' Japanese Journal of Applied Physics, vol. 55, p. 04EG02, 2016. [53] P.-C. Chen, Y.-H. Wu, Z.-W. Zheng, Y.-C. Chiu, C.-H. Cheng, S.-S. Yen, et al., 'Bipolar Conduction in Tin-Oxide Semiconductor Channel Treated by Oxygen Plasma for Low-Power Thin-Film Transistor Application,' Journal of Display Technology, vol. 12, pp. 224-227, 2016. [54] J.-H. Lee, Y.-J. Choi, C.-Y. Jeong, D.-K. Jung, S. Ham, and H.-I. Kwon, 'Electrical Instability of P-channel SnO Thin-Film Transistors Under Light Illumination,' IEEE Electron Device Letters, vol. 37, pp. 295-298, 2016. [55] S. J. Han, S. Kim, J. Ahn, J. K. Jeong, H. Yang, and H. J. Kim, 'Composition-Dependent Structural and Electrical Properties of P-type SnOx Thin Films Prepared by Reactive DC Magnetron Sputtering: Effects of Oxygen Pressure and Heat Treatment,' RSC Advances, vol. 6, pp. 71757-71766, 2016. [56] Y. Chiu, P. Chen, S. Chang, Z. Zheng, C. Cheng, G. Liou, et al., 'Channel Modification Engineering by Plasma Processing in Tin-Oxide Thin Film Transistor: Experimental Results and First-Principles Calculation,' ECS Journal of Solid State Science and Technology, vol. 6, pp. Q53-Q57, 2017. [57] S. H. Kim, I.-H. Baek, D. H. Kim, J. J. Pyeon, T.-M. Chung, S.-H. Baek, et al., 'Fabrication of High-Performance P-type Thin Film Transistors Using Atomic-Layer-Deposited SnO Films,' Journal of Materials Chemistry C, vol. 5, pp. 3139-3145, 2017. [58] L. Qiang, W. Liu, Y. Pei, G. Wang, and R. Yao, 'Trap States Extraction of P-channel SnO Thin-Film Transistors Based on Percolation and Multiple Trapping Carrier Conductions,' Solid-State Electronics, 2016. [59] Y.-J. Choi, Y.-J. Han, C.-Y. Jeong, S.-H. Song, G. W. Baek, S. H. Jin, et al., 'Enhancement Mode p-Channel SnO Thin-Film Transistors with Dual-Gate Structures,' Journal of Vacuum Science Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 33, p. 041203, 2015. [60] C.-W. Zhong, H.-C. Lin, K.-C. Liu, and T.-Y. Huang, 'Improving Electrical Performances of P-type SnO Thin-Film Transistors Using Double-Gated Structure,' IEEE Electron Device Letters, vol. 36, pp. 1053-1055, 2015. [61] R. Hattori and J. Kanicki, 'Contact Resistance in Schottky Contact Gated-Four-Probe a-Si Thin-Film Transistor,' Japanese Journal of Applied Physics, vol. 42, pp. L907-L909, 2003. [62] W. Wang, L. Li, C. Lu, Y. Liu, H. Lv, G. Xu, et al., 'Analysis of the Contact Resistance in Amorphous InGaZnO Thin Film Transistors,' Applied Physics Letters, vol. 107, p. 063504, 2015. [63] J. Jeong, J. Kim, G. Jun Lee, and B.-D. Choi, 'Intrinsic Parameter Extraction of a-InGaZnO Thin-Film Transistors by a Gated-Four-Probe Method,' Applied Physics Letters, vol. 100, p. 023506, 2012. [64] J. Jeong, G. Jun Lee, J. Kim, S. Moon Jeong, and J.-H. Kim, 'Analysis of Temperature-Dependent Electrical Characteristics in Amorphous In-Ga-Zn-O Thin-Film Transistors Using Gated-Four-Probe Measurements,' Journal of Applied Physics, vol. 114, p. 094502, 2013. [65] 鄭湘原, 李嘉平, and 羅正忠, '半導體工程─導先進製程與模擬,' ed: 普林斯頓, 2002. [66] 張勁燕, '半導體製程設備,' 2005. [67] R. A. Surmenev, 'A Review of Plasma-Assisted Methods for Calcium Phosphate-Based Coatings Fabrication,' Surface and Coatings Technology, vol. 206, pp. 2035-2056, 2012. [68] R. W. Johnson, A. Hultqvist, and S. F. Bent, 'A Brief Review of Atomic Layer Deposition: from Fundamentals to Applications,' Materials Today, vol. 17, pp. 236-246, 2014. [69] https://www.jeol.co.jp/en/science/eb.html, 20170625. [70] 林麗娟, 'X 光繞射原理及其應用.' [71] 'http://jacobs.physik.uni-saarland.de/english/instrumentation/uhvl.htm,' 20170630. [72] P. Barquinha, A. Pimentel, A. Marques, L. Pereira, R. Martins, and E. Fortunato, 'Influence of the Semiconductor Thickness on the Electrical Properties of Transparent TFTs Based on Indium Zinc Oxide,' Journal of Non-Crystalline Solids, vol. 352, pp. 1749-1752, 2006. [73] Y. Wang, X. W. Sun, G. K. L. Goh, H. V. Demir, and H. Y. Yu, 'Influence of Channel Layer Thickness on the Electrical Performances of Inkjet-Printed In-Ga-Zn Oxide Thin-Film Transistors,' IEEE Transactions on Electron Devices, vol. 58, pp. 480-485, 2011. [74] J.-S. Park, J. K. Jeong, Y.-G. Mo, H. D. Kim, and C.-J. Kim, 'Control of Threshold Voltage in ZnO-Based Oxide Thin Film Transistors,' Applied Physics Letters, vol. 93, p. 033513, 2008. [75] https://en.wikipedia.org/wiki/Work_function, 20170630. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/68539 | - |
dc.description.abstract | 本研究在玻璃基板上開發單閘極與雙閘極氧化亞錫薄膜電晶體,並利用四端(gated-four probe)量測分析其電性。首先,透過主動層厚度的調變以及主動層後退火處理,成功提升單閘極氧化亞錫薄膜電晶體之載子遷移率。接著,透過四端量測對主動層的本質電性以及接觸電阻進行探討,並將最佳化之製程參數應用到雙閘極薄膜電晶體製作上,並針對上閘極材料以及操作模式對元件特性影響進行分析,最終利用上閘極有效調控臨界電壓。 實驗中利用射頻磁控濺鍍系統在室溫下,透過金屬錫靶材製備厚度分別為15、17.5和20 nm的氧化亞錫薄膜,接著在空氣環境下進行225℃退火0.5、1、2、3和5分鐘。由低掠角X光繞射頻譜發現氧化亞錫薄膜厚度17.5 nm搭配退火3分鐘條件下,具最顯著(101)晶相。而在成分分析上,X光光電子能譜分析顯示隨著退火時間的增長,薄膜中金屬錫Sn0+的比例隨之下降,四價錫Sn4+的比例隨之上升。在相同退火時間下,較薄之薄膜成分較偏向四價錫Sn4+,而較厚的薄膜則較偏向金屬錫Sn0+。 在下閘極結構之薄膜電晶體電性方面,當主動層厚度為17.5 nm時,隨著退火時間的增加非本質(即場效)載子遷移率會先增而後減,最高非本質載子遷移率發生在退火條件為3分鐘,達2.65 cm2/V∙s,此與其結晶性與成分比例有明顯相關性。研究中也觀察到隨著主動層厚度增加,其達到最佳非本質載子遷移率的退火時間亦漸增,例如主動層厚度為15 nm時,最佳非本質載子遷移率發生在退火時間為2分鐘的條件下,達到1.64 cm2/V∙s;而厚度為20 nm時,則在退火時間為5分鐘時達到最佳非本質載子遷移率的2.06 cm2/V∙s。此外,我們透過四端量測分析其薄膜電晶體之本質載子遷移率、通道本質電阻以及接觸電阻,發現在最佳條件下(厚度17.5 nm、退火3分鐘)擁有最低的通道本質電阻及接觸電阻。而當非本質載子遷移率越高時,所量測出來的本質載子遷移率也會越高,且兩者間的差異與接觸電阻相關,同時較高的接觸電阻亦伴隨著最低的載子遷移率。 最後我們將具最佳化之主動層製程參數(厚度17.5 nm、退火3分鐘)的下閘極氧化亞錫薄膜電晶體應用至雙閘極薄膜電晶體上。結果發現,使用功函數較小的上閘極材料,能降低電晶體臨界電壓之絕對值,故在操作模式研究中採用金屬鈦為上閘極材料。當上閘極施加偏壓由 0 V增加至4 V時,以下閘極操作薄膜電晶體,臨界電壓可由2.13 V降低至 0.83 V;而在雙閘極同時操作的情形下,能夠使其開電流提升,且其電流開關比達四個數量級。此雙閘極結構能夠藉由不同的操作模式調變薄膜電晶體臨界電壓並提升其電性。 | zh_TW |
dc.description.abstract | In the research, we demonstrated single-gate and double-gate tin monoxide (SnO) thin film transistors (TFTs), and characterized the electrical performance by gated-four probe measurement. First, we investigated the effect of thickness and annealing time of the SnO channel on the electrical performance of single-gate TFTs. Gate-four probe measurements were carried out to evaluate the channel resistance and contact resistance. Next, the optimal condition obtained is applied to the double-gate SnO TFTs. The influence of the top-gate material and the operation mode on the electrical characteristics of double-gate TFTs was studied. SnO thin films of 15, 17.and 20 nm were deposited by reactive rf-sputtering at room temperature using a metal tin target, followed by an annealing process at 225℃ in air ambient for 0.5, 1, 2, 3 and 5 min. The glancing-angle X-ray diffraction spectra show that the 17.5 nm SnO film with an annealing time of 3 min exhibits the strongest (101) diffraction peak among all. The X-ray photoelectron spectroscopy analysis shows that as the annealing time of the SnO thin film increases the amount of metallic Sn decreases and the amount of Sn4+ increases. For the same annealing time, the thinner film contains more Sn4+ and the thicker film has more metallic Sn. For the bottom-gate SnO TFT with 17.5 nm-thick channel layer, the extrinsic (linear field-effect) mobility increases first and then decreases as the annealing time increases. The optimal extrinsic mobility reached 2.65 cm2/V∙s when the annealing time is 3 min. The electrical performance is highly dependent on the crystalline phase and content of the SnO channel. In addition, as the thickness of the SnO channel layer increases, the optimal annealing time increases. For instance, the optimal annealing times for the 15-nm-thick and 20-nm-thick SnO channel layers are 2 and 5 min, respectively, and the corresponding linear mobilities achieved are 1.64 and 2.06 cm2/V∙s. The intrinsic mobility, intrinsic channel resistance and contact resistance were analyzed by gated-four probe measurements. We found that the lowest channel resistance and the contact resistance was obtained in the optimal condition. Besides, when the extrinsic mobility is higher, the higher intrinsic mobility can be measured. The difference between extrinsic and intrinsic mobility is correlated with contact resistance. In the meantime, the lower contact resistance is, the higher mobility of TFT can be. Finally, the optimal condition of bottom-gate SnO TFT obtained is then applied to the double-gate SnO TFT. By using different top-gate metal material, the threshold voltage of the bottom-gate mode can be modulated. The lower the work function of top metal gate, the smaller the threshold voltage. Therefore, Ti is chosen as the top gate material for the subsequent experiments. As the bias voltage of the top gate increases from 0 to +4 V, the threshold voltage of the bottom-gate mode decreases from 2.13 V to 0.83 V. In the dual-gate operation mode, on-current were enhanced and on/off ratio of > 104 were obtained. The results show that the threshold voltage can be modulated and the electrical performance can be improved by using a double-gate architecture. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T02:24:33Z (GMT). No. of bitstreams: 1 ntu-106-R04941077-1.pdf: 5487960 bytes, checksum: 6d939729a30653cd4d738c0515e7abee (MD5) Previous issue date: 2017 | en |
dc.description.tableofcontents | 目錄 致謝 I 中文摘要 II Abstract IV 目錄 VI 圖目錄 IX 表目錄 XV 第一章 緒論 1 1.1 薄膜電晶體的發展與背景 1 1.2 研究動機 3 1.3 論文架構 4 第二章 理論與文獻回顧 6 2.1 薄膜電晶體簡介 6 2.1.1 薄膜電晶體之結構 6 2.1.2 薄膜電晶體之操作原理 8 2.1.3 薄膜電晶體之特徵參數 9 2.1.4 薄膜電晶體之介電層電性分析 13 2.2 p型金屬氧化物半導體簡介 13 2.2.1 p型金屬氧化物半導體之材料 14 2.2.2 氧化亞錫之基本特性 16 2.3 氧化亞錫薄膜電晶體之文獻回顧 23 2.3.1 單閘極薄膜電晶體 23 2.3.2 雙閘極薄膜電晶體 35 2.4 四端(Gated-four-probe)量測之簡介以及文獻回顧 37 2.4.1 四端量測之簡介 37 2.4.2 四端量測之文獻回顧 43 第三章 實驗方法與步驟 45 3.1 薄膜沉積方法 45 3.1.1 射頻磁控濺鍍系統 45 3.1.2 原子層沉積系統 47 3.1.3 電子束蒸鍍系統 49 3.2 微影製程 50 3.3 蝕刻製程 52 3.3.1 濕式蝕刻製程 52 3.3.2 乾式蝕刻製程 52 3.4 MIM結構製備流程 53 3.5 氧化亞錫薄膜電晶體製備流程 54 3.5.1 單閘極四端(gated-four probe)氧化亞錫薄膜電晶體 54 3.5.2 雙閘極四端(gated-four probe)氧化亞錫薄膜電晶體 56 3.6 薄膜特性分析 57 3.6.1 薄膜X射線繞射儀 57 3.6.2 X射線光電子能譜分析儀 59 3.7 薄膜電晶體特性量測方法 61 3.7.1 電容-電壓量測方法 61 3.7.2 單閘極薄膜電晶體特性量測方法 61 3.7.3 雙閘極薄膜電晶體特性量測方法 63 第四章 結果與討論 65 4.1 氧化亞錫薄膜分析 65 4.1.1 不同製程條件下氧化亞錫薄膜之結晶性 65 4.1.2 不同製程條件下X射線光電子能譜之分析 67 4.2 二氧化鉿介電層電容電壓特性分析 71 4.3 單閘極氧化亞錫薄膜電晶體元件特性分析 72 4.3.1 不同製程條件下單閘極氧化亞錫薄膜電晶體特性分析 72 4.3.2 不同製程條件下單閘極四端氧化亞錫薄膜電晶體之分析 81 4.4 雙閘極氧化亞錫薄膜電晶體 88 4.4.1 不同上閘極材料對雙閘極薄膜電晶體的影響 88 4.4.2 不同操作模式對雙閘極薄膜電晶體的影響 91 4.4.3 上閘極偏壓對雙閘極薄膜電晶體的影響 98 第五章 結論與未來展望 99 5.1 結論 99 5.2 未來展望 101 A 附錄 102 I. 以Transmission line measurement (TLM) 分析氧化亞錫薄膜電晶體的接觸電阻以及單位長度通道電阻 102 參考文獻 104 | |
dc.language.iso | zh-TW | |
dc.title | 利用四端量測分析單閘極與雙閘極氧化亞錫薄膜電晶體之電性 | zh_TW |
dc.title | Characterization of P-Type Single-Gate and Double-Gate Tin Monoxide Thin-Film Transistors Using Gated-Four-Probe Measurements | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳建彰(Jian-Zhang Chen),吳志毅(Chih-I Wu),吳肇欣(Chao-Hsin Wu) | |
dc.subject.keyword | 四端量測,雙閘極,氧化亞錫,p型氧化物半導體,薄膜電晶體, | zh_TW |
dc.subject.keyword | gated-four probe measurements,double gate,tin monoxide,p-type oxide semiconductor,thin-film transistor, | en |
dc.relation.page | 110 | |
dc.identifier.doi | 10.6342/NTU201703843 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2017-08-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 光電工程學研究所 | zh_TW |
顯示於系所單位: | 光電工程學研究所 |
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