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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚(Chung-Yang (Ric) | |
| dc.contributor.author | Yo-Chi Lee | en |
| dc.contributor.author | 李友岐 | zh_TW |
| dc.date.accessioned | 2021-05-11T04:56:13Z | - |
| dc.date.available | 2019-08-13 | |
| dc.date.available | 2021-05-11T04:56:13Z | - |
| dc.date.copyright | 2019-08-13 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-08-10 | |
| dc.identifier.citation | [1] Kuochun Lee, Tsung-Yen Chen, “Automatic engineering change order methodology,” U.S. Patent 6 453 454, September 17, 2002.
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Huang, “Match and replace: A functional ECO engine for multi-error circuit rectification,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no.3, pp. 467-478, March 2013. [8] Chia-Lin Hsieh, “Semi-Formal ECO Method,” Master Thesis, Graduate Institute of Electronics Engineering, College of Electrical Engineering and Computer Science, National Taiwan University, Jul. 2018. https://hdl.handle.net/11296/g3b8pj [9] N. So ̈ rensson and N. Ee ́ , “Minisat v1. 13: A SAT solver with conflict-clause minimization,” in Proc. SAT, pp. 53–54, 2005. [10] D. Brand, “Verification of large synthesized designs,” in Proc. IEEE/ACM ICCAD, pp. 534–537, Nov. 1993. [11] A. Mishchenko, S. Chatterjee, and R. Brayton, “Fraigs: A unifying representation for logic synthesis and verification,” EECS Dept., UC Berkeley, Tech. Rep, 2005. [12] M. Abadir, J. Ferguson, and T. Kirkland, “Logic design verification via test generation,” IEEE Trans. Comput.-Aided Design Integr. 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Bertacco, “Fixing design errors with counterexamples and resynthesis,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 1, pp. 184–188, Jan. 2008. [19] K.-F. Tang, C.-A. Wu, P.-K. Huang, and C.-Y. Huang, “Interpolation-based incremental ECO synthesis for multi-error logic rectification,” in Proc. 48th ACM/EDAC/IEEE DAC, pp. 146–151, Jun. 2011. [20] K.-F. Tang, P.-K. Huang, C.-N. Chou and C.-Y. Huang, 'Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction,' Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1567-1572, 2012. [21] S.-Y. Huang, K.-C. Chen, and K.-T. Cheng, “Autofix: A hybrid tool for automatic logic rectification,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 9, pp. 1376–1384, Sep. 1999. [22] D. Hoffmann and T. Kropf, “Efficient design error correction of digital circuits,” in Proc. ICCD, pp. 465–472, Sep. 2000. [23] D. Brand, “Incremental synthesis,” in Proc. IEEE/ACM ICCAD, pp. 14–18, Nov. 1994. [24] S. Krishnaswamy, H. Ren, N. Modi, and R. Puri, “DeltaSyn: An efficient logic difference optimizer for ECO synthesis,” in Proc. IEEE/ACM ICCAD, pp. 789–796, Nov. 2009. [25] A. Kuehlmann and F. Krohm, “Equivalence checking using cuts and heaps,” in Proc. 34th ACM/IEEE DAC, pp. 263–268, Jun. 1997. [26] Q. Zhu, N. Kitchen, A. Kuehlmann, and A. Sangiovanni-Vincentelli, “SAT sweeping with local observability don’t-cares,” in Proc. 43rd ACM/IEEE DAC, pp. 229–234, Jul. 2006. [27] ABC: A system for sequential synthesis and verification. Berkeley Logic Synthesis and Verification Group. http://www-cad.eecs.berkeley.edu/~alanmi/abc [28] A. Biere, “The AIGER And-Inverter Graph (AIG) format version 20071012” in Technical report FMV Reports Series Institute for Formal Models and Verification, Johannes Kepler University, 2007. http://fmv.jku.at/papers/Biere-FMV-TR-07-1.pdf [29] M. Soeken, “IWLS 2017 Programming Contest: Y Logic Synthesis,” 2017. https://github.com/msoeken/iwls2017-contest [30] L.Amaru ́ , P.-E.Gaillardon, and G.DeMicheli, “The epfl combinational benchmark suite,” in Proc. 24th International Workshop on Logic & Synthesis (IWLS), no. EPFL-CONF-207551, 2015. https://lsi.epfl.ch/page-102566-en-html/benchmarks/ | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/handle/123456789/678 | - |
| dc.description.abstract | 在晶片設計的流程中,如果流程後期需要修改原本的電路設計,工程變更指令是一個普遍使用的方法。我們提出新的演算法以優化基於後向切割的工程變更指令引擎效能。我們藉著後向切割在兩個電路中找出改正配對,接著精鍊這些配對以去除多餘的部份。實驗結果顯示我們提出的演算法不但減少了修補邏輯電路的成本也降低了程式運行的時間。除此之外,我們進一步將後向切割應用於等效驗證,實驗結果說明了我們的演算法是可行的。 | zh_TW |
| dc.description.abstract | Engineering change order (ECO) is a popular approach for rectifying circuit errors and specification changes in late design stages. Backward-cut-based ECO solves the problem by divide and conquer from the output side to input side. In this thesis, we present new algorithms to optimize the performance of ECO engine. We first discover the rectification pairs in two circuits by backward-cut approach and then remove the redundant parts by refinement technique. The experimental results show that our algorithm not only reduce the patch circuit cost but also improve the run time of ECO engine. Moreover, we further apply backward-cut approach to the Equivalence Checking (EC) and experimental results prove that our algorithms work. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-11T04:56:13Z (GMT). No. of bitstreams: 1 ntu-108-R06921048-1.pdf: 2709836 bytes, checksum: f8e7fb229536106d43da39fdb8e6a0b4 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 摘要 (i)
ABSTRACT (ii) CONTENT (iii) LIST OF FIGURES (v) LIST OF TABLES (vii) Chapter 1 Introduction (1) Chapter 2 Preliminaries (6) 2.1 Boolean Satisfiability (6) 2.2 Equivalence Checking (EC) & Miter (6) 2.3 AIG, Strash & FRAIG (7) 2.4 Boolean Matching (9) 2.5 Previous Works on Functional ECO (10) 2.6 ECO Problem Formulation and Optimization Criteria (16) 2.7 Rectification Pair (17) 2.8 Cut Function (19) 2.9 Similarity between the Candidate Gates (21) 2.10 Output-side Frontier Identification (22) Chapter 3 Backward-Cut-Based ECO Engine (23) 3.1 Overview of Our ECO Engine (23) 3.2 Merging Phase - Input Side Patch Frontier Identification (25) 3.3 Matching Phase - Output Side Patch Frontier Identification (26) 3.3.1 Cut Matching Algorithm (27) 3.3.2 Rectification Pair Refinement Algorithm (30) 3.3.3 Advanced (Further) Cut Matching Approach (32) 3.4 Repeatedly Solving ECO Algorithm (35) Chapter 4 Backward-Cut-Based EC Algorithm (36) Chapter 5 Experimental Results (38) 5.1 ECO (38) 5.2 EC (47) Chapter 6 Case Study (49) Chapter 7 Conclusion and Future Work (53) REFERENCE (54) | |
| dc.language.iso | en | |
| dc.subject | 等效驗證 | zh_TW |
| dc.subject | 工程變更指令 | zh_TW |
| dc.subject | 後向切割 | zh_TW |
| dc.subject | 修補邏輯電路 | zh_TW |
| dc.subject | backward-cut | en |
| dc.subject | Engineering change order | en |
| dc.subject | equivalence checking | en |
| dc.subject | patch circuit | en |
| dc.title | 基於後向切割的等效驗證和工程變更指令演算法之最佳化 | zh_TW |
| dc.title | Optimizing Backward-Cut-Based EC and ECO Algorithms | en |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李建模(Chien-Mo LI),許智仁(Chih-Jen (Jacky) | |
| dc.subject.keyword | 工程變更指令,後向切割,修補邏輯電路,等效驗證, | zh_TW |
| dc.subject.keyword | Engineering change order,backward-cut,patch circuit,equivalence checking, | en |
| dc.relation.page | 58 | |
| dc.identifier.doi | 10.6342/NTU201902346 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2019-08-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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| ntu-108-1.pdf | 2.65 MB | Adobe PDF | 檢視/開啟 |
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