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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 江介宏(Jie-Hong Roland Jiang) | |
| dc.contributor.author | Chun-Hong Shih | en |
| dc.contributor.author | 施淳浤 | zh_TW |
| dc.date.accessioned | 2021-06-17T01:53:16Z | - |
| dc.date.available | 2018-07-27 | |
| dc.date.copyright | 2017-07-27 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2017-07-24 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/67843 | - |
| dc.description.abstract | 現今的積體電路設計中，非同步電路的設計方法得到越來越多的重視。非同步電路的週期分析、死鎖(deadlock)驗證和優化在電路合成中都是非常重要的議題。以電路週期分析而言，線性規劃分析(linear programing based analysis)和靜態效能分析(static performance analysis)是現有做法中的兩個重要代表。線性規劃分析是高精度但低效率的，另外其分析結果是否符合實際電路的運作仍是未知。現今的靜態效能分析是高效率的，然而先前方法僅侷限於無環管線(acyclic pipeline)電路，並不能應用於有環管線(cyclic pipeline)電路的分析，且其精度還有待改進。此外，它在電路漸進式優化(incremental optimization)的應用上，效能分析必須被大量的重複使用，而先前的效能分析方法未針對漸進式優化的應用加以改良以至於非常沒有效率。在本論文中，我們展示了線性規劃分析的結果在某些情況下並不會在實際電路中發生，因而線性規劃分析的週期有可能低於實際值，我們因而解決了此一未知問題。此外，我們強化了靜態性能分析，使其能運用在有環管線電路而且適用在漸進式電路優化。另外，我們開發了一個應用於有環管線電路的死鎖驗證流程。我們進一步將這篇論文中提出的效能分析與死鎖驗證技術應用於電路的面積和效能優化。實驗結顯示我們的改進及泛化後的靜態效能分析總是得到精確的週期時間，其運算速度比線性規劃分析快了高達4000倍。此外，透過相對應的優化流程，電路面積平均可以減少19％，而電路效能也有顯著的改進。 | zh_TW |
| dc.description.abstract | Asynchronous methodologies are gaining their presence in modern integrated circuit design. Cycle-time analysis, deadlock verification, and performance optimization are crucial to circuit synthesis. Among prior methods, linear programming-based analysis (LPA) and static performance analysis (SPA) are two representatives with high accuracy (but inefficient) and high efficiency (but inaccurate), respectively. However, the exactness of LPA remains unknown. Prior SPA can not be applied in cyclic circuits and its accuracy remains room for improvement. Moreover, SPA is not practical for incremental analysis in optimization iterations. In this thesis, we demonstrate the inexactness of LPA and enhance SPA to overcome its weakness. Also, we develop an efficient synthesis flow for deadlock verification in cyclic asynchronous pipelines and perform circuit optimization for area reduction and cycle-time improvement. Experimental results suggest our enhanced SPA almost always returns exact cycle-times while achieving up to 4000x speedup over LPA. Moreover, we conducted incremental logic transformation yielding an average of 19\% area reduction and iterative performance optimization with notable cycle time improvement. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T01:53:16Z (GMT). No. of bitstreams: 1 ntu-105-R04943088-1.pdf: 6882905 bytes, checksum: 72b39979fe0db7acaffe6a8a302d0931 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | Acknowledgements iii
Abstract vi List of Figures xi List of Tables xiv 1 Introduction 1 1.1 Our Contributions . . . . . . . . . . . . . . . . . . . . . 4 1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . 5 2 Preliminary 6 2.1 Quasi-Delay Insensitive Model . . . . . . . . . . . . . . . 6 2.2 Four-phase Protocol . . . . . . . . . . . . . . . . . . . . 7 2.3 Physical Implementation and Abstract Model of QDI Circuits 8 2.4 Pipeline Modeling . . . . . . . . . . . . . . . . . . . . . 11 2.5 Cycle-Time Analysis . . . . . . . . . . . . . . . . . . . . 12 3 Discussion of SPA and LPA 16 3.1 Difference between SPA and LPA . . . . . . . . . . . . . . 16 3.2 SPA Over-Estimation . . . . . . . . . . . . . . . . . . . . 19 3.3 LPA Under-Estimation . . . . . . . . . . . . . . . . . . . 20 4 Generalization and Improvement of Static Performance Analysis 23 4.1 Static Performance Analysis for Cyclic Pipelines . . . . . 24 4.1.1 Register Modeling . . . . . . . . . . . . . . . . . . . . 24 4.1.2 Static Performance Analysis . . . . . . . . . . . . . . . 26 4.1.3 Experimental result . . . . . . . . . . . . . . . . . . . 34 4.2 Incremental Static Performance Analysis . . . . . . . . . . 35 4.2.1 Incremental Analysis for Buffer Insertion . . . . . . . . 39 4.2.2 Incremental Analysis for Buffer Removal . . . . . . . . . 39 4.2.3 Incremental Analysis for Evaluation Time Change . . . . . 40 4.2.4 Incremental Analysis for Pre-Charge Time Change . . . . . 40 4.3 SPA Accuracy Enhancement . . . . . . . . . . . . . . . . . 41 4.3.1 Incremental Analysis . . . . . . . . . . . . . . . . . . 43 4.3.2 Critical Input Analysis . . . . . . . . . . . . . . . . . 44 4.3.3 Experimental Result . . . . . . . . . . . . . . . . . . . 45 5 Deadlock Verification 58 5.1 Deadlock Detection . . . . . . . . . . . . . . . . . . . . 58 5.2 Deadlock Removal . . . . . . . . . . . . . . . . . . . . . 62 6 Asynchronous Circuit Optimization 64 6.1 Area Optimization . . . . . . . . . . . . . . . . . . . . . 64 6.1.1 Experimental Result . . . . . . . . . . . . . . . . . . . 65 6.2 Performance Optimization . . . . . . . . . . . . . . . . . 67 6.2.1 Cycle Time Effect of Buffer Insertion . . . . . . . . . . 68 6.2.2 Cycle Time Effect of Buffer Removal . . . . . . . . . . . 71 6.2.3 Cycle Time Effect of Evaluation Time Change . . . . . . . 74 6.2.4 Cycle Time Effect of Pre-Charge Time Change . . . . . . . 75 6.2.5 Performance Optimization Via Buffer Insertion and Removal 77 6.2.6 Experimental Result . . . . . . . . . . . . . . . . . . . 79 7 Conclusions 82 Bibliography 84 | |
| dc.language.iso | en | |
| dc.subject | 非同步電路 | zh_TW |
| dc.subject | 靜態效能分析 | zh_TW |
| dc.subject | 線性規劃分析 | zh_TW |
| dc.subject | 效能優化 | zh_TW |
| dc.subject | 有環管線電路 | zh_TW |
| dc.subject | 死鎖 | zh_TW |
| dc.subject | deadlock | en |
| dc.subject | static performance analysis | en |
| dc.subject | performance optimization | en |
| dc.subject | asynchronous circuits | en |
| dc.subject | cyclic pipeline | en |
| dc.subject | linear programming-based analysis | en |
| dc.title | 非同步電路優化靜態性能分析的泛化與改進 | zh_TW |
| dc.title | Generalization and Improvement of Static Performance Analysis for Asynchronous Circuit Optimization | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉宗德(Tsung-Te Liu),楊家驤(Chia-Hsiang Yang),鄭福炯(Fu-Chiung Cheng),江蕙如(Iris Hui-Ru Jiang) | |
| dc.subject.keyword | 非同步電路,靜態效能分析,線性規劃分析,效能優化,有環管線電路,死鎖, | zh_TW |
| dc.subject.keyword | asynchronous circuits,static performance analysis,linear programming-based analysis,performance optimization,cyclic pipeline,deadlock, | en |
| dc.relation.page | 90 | |
| dc.identifier.doi | 10.6342/NTU201701747 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2017-07-24 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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