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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/67729完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李致毅(Jri Lee) | |
| dc.contributor.author | Jian-Xun Yu | en |
| dc.contributor.author | 余建勳 | zh_TW |
| dc.date.accessioned | 2021-06-17T01:46:30Z | - |
| dc.date.available | 2017-07-28 | |
| dc.date.copyright | 2017-07-28 | |
| dc.date.issued | 2017 | |
| dc.date.submitted | 2017-07-26 | |
| dc.identifier.citation | [1] Adrian Maxim et al., “A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1673-1683, Nov. 2001.
[2] Jaeha Kim et al., “A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 899-908, Apr. 2006. [3] J. Lee, “High-speed circuit designs for transmitters in broadband data links,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1004-1015, May 2006. [4] Remco C. H. van de Beek et al., “A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1862-1872, Nov. 2004. [5] Richard Gu et al., “A 6.25 GHz 1 V LC-PLL in 0.13-μm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 594-595. [6] Alan W.L. Ng et al., “A 1V 24GHz 17.5mW PLL in 0.18μm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 158-159 and pp. 590. [7] D. Park and S. Mori, “Fast acquisition frequency synthesizer with the multiple phase detectors,” in 1991 IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing Conf. Proc., May 1991, vol. 2, pp. 665-668. [8] T. Lee and W. Lee, “A spur suppression technique for phase-locked frequency synthesizers,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 2432-2441. [9] B. Razavi, RF Microelectronics., Second Edition, Prentice-Hall, 2012. [10] J. Lee, course lecture: Design of Communication Integrated Circuits, chapter 8. [11] I. M. Filanovsky and A. Allam, “Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits,” IEEE Trans. Circuits Syst. I, vol. 48, no. 7, pp. 876–884, Jul. 2001. [12] J. Lee et al., “A 75-GHz phase-locked loop in 90-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 43, pp. 1414-1426, June 2008. [13] C. S. Vaucher and D. Kasperkovitz, “A wide-band tuning system for fully integrated satellite receivers,” IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 987-998, July 1998. [14] M. H. Perrot, T. T. Tewksbury, and C. G. Sodini, “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation,” IEEE J. Solid- State Circuits, vol. 32, no. 12, pp. 2048–2060, Dec. 1997. [15] B. Miller and R. Conley, “A multiple modulator fractional divider,” in Proc. 44th Annu. Frequency Control Symp., May 1990, pp. 559–568. [16] Gyu-Seob Jeong et al., “A 0.015-mm2 inductorless 32-GHz clock generator with wide frequency-tuning range in 28-nm CMOS technology,” IEEE Trans. Circuits Syst. II, vol. 64, no. 6, pp. 655–659, June 2017. [17] A. Li, S. Zheng, J. Yin, X. Luo, and H. C. Luong, “A 21–48 GHz subharmonic injection-locked fractional-N frequency synthesizer for multiband point-to-point backhaul communications,” IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1785–1799, Aug. 2014. [18] J.-C. Chien et al., “A pulse-position-modulation phase-noise-reduction technique for a 2-to-16 GHz injection-locked ring oscillator in 20 nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 52–53. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/67729 | - |
| dc.description.abstract | 現今的無線通信更加注重高速率和寬頻帶的需要。在Ka波段的PLL，所有模塊裡傳統寬帶操作最關鍵的是VCO和除頻器，佔用大面積和高功耗。本論文提出了一個頻率範圍為20-40GHz的分數型時脈產生器。此電路包括帶隙參考、相位檢測器、環路濾波器、VCO和由四/五級串聯的2/3除頻器所構成的多模數除頻器，總共除頻範圍為20-40。 PLL晶片採用40nm CMOS技術製造，尺寸為1.92×0.88 mm2，分別從1.2 V，1.5 V，1 V和2.5 V電源消耗220 mA，46 mA，7 mA和4mA電源，總功耗為0.35W。相位噪聲在與載波1MHz偏移處測量為-100.4dBc / Hz，均方根抖動為400fs。為了選擇正確的輸出頻率，內建了兩種的頻段選擇機制，都可以選擇正確的VCO和頻帶。為了最小化抖動，我們可以通過不同的電荷幫浦電流來改變環路帶寬。 | zh_TW |
| dc.description.abstract | Nowadays, wireless communication gets more attention to the demand of high rate and wide band. In a Ka-band PLL, the traditional VCO and frequency divider are the most critical to the broadband operation among all modules and occupy large silicon area and high power consumption. This thesis presents a fractional-N phase-locked loop (PLL) with a tuning range of 20-40GHz. The frequency synthesizer includes bandgap reference, phase detector, loop filter, VCO, and multimodulus divider with four/five cascaded 2/3 dividers that give an overall divide range of 20~40 in TSMC 40-nm CMOS technology. The PLL chip is fabricated in a 40-nm CMOS technology, measures 1.92×0.88 mm^2, and consumes 220 mA, 46 mA, 7 mA, and 4mA from a 1.2 V, 1.5 V, 1 V, and 2.5 V power supply, respectively, for a total power consumption of 0.35 W. The phase noise is measured to be -100.4dBc/Hz at 1 MHz offset from the carrier and root-mean-square jitter is 400fs. To choose the correct output frequency, two type of band selection mechanism are build and both can choose the right VCO and frequency band. To minimize the jitter, we can change loop bandwidth by different charge bump current. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T01:46:30Z (GMT). No. of bitstreams: 1 ntu-106-R03943125-1.pdf: 3940567 bytes, checksum: 3aaef3fefa88f2bbe7cbd0bbe042c88c (MD5) Previous issue date: 2017 | en |
| dc.description.tableofcontents | 口試委員會審定書.............................#
中文摘要....................................i ABSTRACT...................................ii CONTENTS...................................iii LIST OF FIGURES............................v LIST OF TABLES.............................viii Chapter 1 Introduction......................1 1.1 Background and Motivation..............1 1.2 Organization of Thesis.................1 Chapter 2 Introduction of Clock Generator...2 2.1 Basic Principle........................2 2.2 Phase Frequency Detector...............5 2.3 Charge Pump...........................11 2.4 Loop Filter...........................14 2.5 Loop Bandwidth Optimization...........17 2.6 Fractional-N PLLs.....................22 2.7 ΔΣ Modulator..........................24 2.8 Noise Calculation.....................29 Chapter 3 Design of a 625MHz to 40GHz Fractional-N Clock Generator in 40nm CMOS Technology...............34 3.1 Introduction...............................34 3.2 Building Blocks............................36 3.2.1 Single-Sideband Phase Frequency Detector.36 3.2.2 Loop Filter and Charge Pump..............37 3.2.3 Voltage Control Oscillators..............39 3.2.4 Selectors................................41 3.2.5 Divider Chain............................42 3.2.6 CML-to-CMOS converter....................47 3.2.7 ΔΣ ModulatorCML-to-CMOS converter........48 Chapter 4 System Integration....................51 4.1 Single Chip Clock Generator................51 Chapter 5 Experimental Result...................53 5.1 Measurement Setup..........................53 5.2 Module Measurement Results.................55 Chapter 6 Conclusions...........................59 REFERENCE.......................................60 | |
| dc.language.iso | en | |
| dc.subject | 電壓控制震盪器 | zh_TW |
| dc.subject | Ka頻段 | zh_TW |
| dc.subject | Σ-Δ調變器 | zh_TW |
| dc.subject | 金氧半場效電晶體 | zh_TW |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | 頻率合成器 | zh_TW |
| dc.subject | CMOS | en |
| dc.subject | VCO | en |
| dc.subject | Ka-band | en |
| dc.subject | Synthesizer | en |
| dc.subject | Sigma-Delta Modulator | en |
| dc.subject | PLL | en |
| dc.title | 40-GHz 分數型時脈產生器 | zh_TW |
| dc.title | A 40-GHz Fractional-N Clock Generator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),劉宗德(Tsung-Te Liu),彭朋瑞(Pen-Jui Peng) | |
| dc.subject.keyword | Ka頻段,鎖相迴路,金氧半場效電晶體,Σ-Δ調變器,頻率合成器,電壓控制震盪器, | zh_TW |
| dc.subject.keyword | Ka-band,PLL,CMOS,Sigma-Delta Modulator,Synthesizer,VCO, | en |
| dc.relation.page | 62 | |
| dc.identifier.doi | 10.6342/NTU201701940 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2017-07-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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