使用相位追蹤延遲器之寬頻且快速鎖定全數位延遲鎖定迴路

Abstract

在IC設計領域當中，系統層級的整合已經成為現今的主要趨勢。延遲鎖定迴路被廣泛地使用在SoC(System-on-a-Chip)中，用來解決時脈歪斜問題和同步SoC中的每一個知識產權（Intellectual Property）和組件電路。然而，可作為一個IP的類比寬頻延遲鎖定迴路越來越難實現，而且也更難設計於高階製程當中。相較之下，全數位延遲鎖定迴路更容易實現於高階製程中，也易與數位系統整合。這份研究目的即在系統層級中，提出一個可視為IP的寬頻且快速鎖定的全數位延遲鎖定迴路。 此篇論文提出了一個創新電路─相位追蹤延遲器。使用相位追蹤延遲器的目的為取代一般使用在寬頻延遲鎖定迴路中的延遲線，並且將工作頻率範圍拓寬至6.7MHz-1.24GHz。除此之外，使用相位追蹤延遲器和以時脈同步延遲為基礎的控制單元使快速鎖定時間只需5個週期即可達成。有限狀態機和時間至數位轉換器為基礎的控制訊號產生器提供低抖動性能，而操作頻率在1.24GHz時，峰對峰抖動量測結果只有2.22ps。此晶片是使用台積電90nm CMOS製成，其核心電路面積為0.0318平方毫米。

Nowadays, system-level integration has become the main trend in the IC design fields. DLLs are widely used in SoCs for solving the clock skew issues and synchronizing each intellectual property (IP) and module. However, wide-range analog DLLs which could be designed as an IP are becoming harder to be implemented and more difficult to be designed in the advanced processes nowadays. In contrast, the all-digital DLLs (ADDLLs) are easier to be realized and integrated with the digital systems in these advanced processes. A wide-range and fast-locking ADDLL as an IP for the system-level is proposed in this work. In this thesis, a novel phase-tracing delay unit (PTDU) will be proposed as well. The purpose of using a PTDU is to replace with the long delay line which is used in wide-range DLLs and to enlarge the operating frequency range which is over 6.7MHz-1.24GHz. Moreover, the PTDU and the CSD-based control unit achieve fast-locking time which is only 5 cycles. The FSMs and TDC-based code generators provide low jitter performance, which is 2.22ps at 1.24GHz in our measurement. The chip was fabricated in TSMC 90nm CMOS process and occupied 0.0318mm2 active area.