V頻段四倍頻器與K頻段可調式高鏡像抑制正交混頻器 之研製

Abstract

頻率倍頻器為無線通訊系統中一個重要元件，因為高頻的訊號源較難實現，因此通常以一個低頻的壓控振盪器串接一個頻率倍頻器減少實現的困難度和降低相位雜訊。隨著倍頻數的提升，倍頻器的輸出功率會因為高階的諧波項而降低。因此，要設計一個擁有高輸出功率的高階倍頻器是一大挑戰。在本論文，我們利用90-nm 1P9M CMOS製程設計一個V頻段的四倍頻器，希望能設計一個有高轉換增益、諧波抑制和高輸出功率的四倍頻器。我們串接兩個倍頻器和一個緩衝放大器來實現四倍頻器，並且利用3D的螺旋電感來縮小尺寸。最後成功設計出一個擁有不錯輸出功率的四倍頻器。此四倍頻器在66 GHz有3 dB的轉換增益，且3 dB頻寬從60到70 GHz。而在65 GHz有最大的輸出功率4 dBm，並且諧波抑制都小於30 dB。 為了達到良好的鏡像抑制，正交的相位和相等的振幅對於鏡像抑制混頻器是兩個非常重要的因素。不幸地，製程的變異對於設計一個高鏡像抑制的混頻器是一大挑戰。本論文中，我們利用0.18-um 1P6M CMOS製程設計一個高鏡像抑制的混頻器。傳統的正交產生器對於製程的變異相當敏感，例如: poly-phase filter。為了克服製程的變異，我們提出了一個新的正交產生器，可以利用壓控可變電阻來調整相位和振幅的不平衡。可變電阻則是由NMOS並聯電感共振掉寄生電容來實現，最後設計一個電阻式的混頻器來驗證此架構，在18.5到29 GHz鏡像抑制都有大於30 dB，而最大的鏡像抑制有49.9 dB。

Frequency multiplier is an important component in the wireless communication, because the high-frequency sources are difficult to achieve. Therefore, we usually use a low-frequency voltage control oscillator (VCO) cascading with a multiplier to realize the high frequency sources and it also has better phase noise. With the multiple number increases, the output power of the multiplier would decrease gradually because of high order harmonic term. Therefore, it is a big challenge to design a high order multiplier with high output power. In this thesis, a V-band quadrupler is designed and fabricated in the 90-nm 1P9M CMOS technology. The goal of this work is to design a quadrupler with good conversion gain, harmonic suppressions and good output power. Two doublers and a buffer amplifier are cascaded to realize a quadrupler, and three-dimensional spiral inductors are use in this design. The maximum conversion gain is 3 dB at 66 GHz, and 3-dB bandwidth is from 60-to-70 GHz. The maximum output power is 4 dBm at 65 GHz, and harmonic suppressions are all smaller than 30 dB. To achieve good image rejection ratio, a quadrature generator with good phase and amplitude imbalances is very important for an image reject mixer. Unfortunately, the process variation is a big challenge for designing a high image rejection characteristic. In this thesis, a high image rejection mixer is designed and fabricated in the 0.18-um 1P6M CMOS technology. The conventional quadrature phase generator, poly-phase filter, is very sensitive to the process variation. To overcome process variation, a new quadrature phase generator with tunable resistors which can be adjusted by a control voltage to fine tune the phase and amplitude imbalances is proposed. The tunable resistor is implemented by a NMOS paralleled with an inductor to resonate the parasitic capacitor. A resistive mixer is designed to verify this mechanism of the proposed quadrature phase generator. This mixer demonstrates an image rejection ratio (IRR) of larger than 30 dB from 18.5 to 29 GHz, and the maximum IRR is 49.9 dB.