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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66646完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑 | |
| dc.contributor.author | Jung-Hsuan Wu | en |
| dc.contributor.author | 吳榮軒 | zh_TW |
| dc.date.accessioned | 2021-06-17T00:48:31Z | - |
| dc.date.available | 2015-01-17 | |
| dc.date.copyright | 2012-01-17 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-12-12 | |
| dc.identifier.citation | [1] http://www.3gpp.org/ftp/Specs/html-info/36212.htm.
[2] P. Elias, “Coding for Noisy Channels,” Proceeding of the Institute of Radio Engineers Convention Record, part 4, pp. 37-46, 1955. [3] A. J. Viterbi, “Error Bounds for Convolutional Codes and Asymptotically Optimum Decoding Algorithm,” IEEE Trans. Information Theory, vol. IT-13, no.2, pp. 260-269, Apr. 1967. [4] C. Berrou and A. Glavieux, “Near Optimum Error Correcting Coding and Decoding: Turbo-Code,” Proc. IEEE Int. Conf. Communications (ICC), pp.1064-1070, May 1993. [5] S. Benedetto and G. Montorsi, “Design of Parallel Concatenated Convolutional Codes,” IEEE Trans. Communication, vol. 44, no. 5, pp. 591-600, May 1996. [6] L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “ Optimal Decoding of Linear Codes for Minimizing Symbol,” IEEE Trans. Information Theory, no. IT-20, pp. 284-287, Mar. 1974. [7] J. A. Erfanian, S. Pasupathy, and G. Gulak, “Reduced Complexity Symbol Detectors with Parallel Structures for ISI Channels,” IEEE Trans. Communication, vol. 42, no. 2/3/4, pp. 1261-1271, Feb./Mar./Apr. 1994. [8] P. Robertson, E. Villebrun, and P. Honher, “A Comparison of Optimal and Suboptimal MAP Decoding Algorithms Operating in the Log Domain,” Proc. IEEE Int. Conf. Communications (ICC), pp.1009-1013, June 1995. [9] S. A. Barbulescu, “Iterative Decoding of Turbo Codes and Other Concatenated Codes,” PH.D. Dissertation, Univ. South Australia, Adelaide, Australia, 1996. [10] C. Schurgers, F. Catthoor, and M. Engels, “Memory Optimization of MAP Turbo Decoder Algorithm,” IEEE Trans. Very Large Scale Integrated (VLSI) System, vol. 9, no. 2, pp. 305-312, Apr. 2001. [11] D. Lee, and I. Park, “ Low Power Log-MAP Decoding Based on Reduced Metric Memory Access,” IEEE Trans. Circuits and Systems, vol. 53, no. 6, pp. 1244-1253, June 2006. [12] M. A. Bickerstaff, D. Garrett, T. Prokop, C. Thomas, B. Widdup, G. Zhou, L. M. Davis, G. Woodward, C. Nicol, and R.H. Yan, “ A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18 um CMOS,” IEEE J. Solid State Circuits, vol. 37, no. 11, pp. 1555-1564, Nov. 2002. [13] C. C. Lin, Y. H. Shih, H. C. Chang, and C. Y. Lee, “A Low Power Turbo/Viterbi Decoder for 3GPP2 Applications,” IEEE Trans. Very Large Scale Integrated (VLSI) System, vol. 14, no. 4, pp. 426-430, Apr. 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66646 | - |
| dc.description.abstract | 下一個世代的4G通訊系統長期演進技術 (Long Term Evolution),是目前在市場上備受矚目的新一代行動無線寬頻技術,它可以讓電信業者透過較為經濟的方式提供無線寬頻服務,並超越現今3G無線網路的效能、帶來更優異的表現,並且已經正式被第三代行動通訊組織 (Third Generation Partnership Project,簡稱3GPP) 列為全新的無線標準技術。LTE相較於3G 和3.5G 最大的優勢在於高速的資料傳輸速率。
在硬體的實現上,為了要達到高速的傳輸速率,所以通道解碼器必須使用到高度平行化的架構,然而這樣的作法會導致其硬體面積和功率消耗過大。因此我們運用一些低功率的架構來減少記憶體的使用量以達到減少面積和功率消耗。此外,為了使硬體能被有效率的使用,我們也採取了硬體共用來增加硬體面積的使用效率。根據這些想法,我們設計了雙模維特比及渦輪碼的解碼器來降低功率消耗和面積的使用量。 在論文中,我們會先簡介通道編碼在通訊系統中的角色和研究動機,接者介紹迴旋碼和渦輪碼的解碼演算法,以及低功率架構和硬體共用的方式,最後介紹實現的流程和結果。 | zh_TW |
| dc.description.abstract | The next-generation communication system, long term evolution (LTE), is currently the most popular mobile wireless technology in the market. LTE allows wireless service providers to improve the economics of deploying mobile broadband networks. The performance of LTE is better than the today’s 3G or 3.5G wireless network. LTE has already been the new standard of a next-generation communication system announced by the third generation partnership project (3GPP). Compared to the 3G and 3.5G communication systems, the obvious advantage of LTE is its high data rate.
In order to provide high data rate transmission, a parallelized architecture of channel decoder is needed for hardware implementation. However, a highly parallelized architecture will require large power consumption and chip area. So we will use some low power architectures to reduce the memory usage for having a smaller chip area and consuming lower power. Besides, we also use the hardware reused technique to increase the area efficiency. According to the ideas above, we propose a dual mode Viterbi/turbo- code decoder to reduce the power dissipation and area. In this Thesis, we will introduce the channel coding in a communication system briefly first. Then, we explain the decoding algorithms for the convolutional code and turbo-code. And the proposed low power architecture and hardware sharing are described. Finally, the implementation flow and result are depicted. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T00:48:31Z (GMT). No. of bitstreams: 1 ntu-100-P98943001-1.pdf: 1997500 bytes, checksum: 3c9012160a5da19e1f57043fc3392d98 (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | ABSTRACT i
LIST OF FIGURES v LIST OF TABLES vii CHAPTER 1 INTRODUCTION 1 1.1 Overview of FEC in Communication Systems 1 1.2 Motivation and Goal 3 1.3 Thesis Organization 4 CHAPTER 2 COVOLUTIONAL CODE AND VITERBI ALGORITHM 5 2.1 Convolutional Code 5 2.1.1 Concept of Convolutional Code 5 2.1.2 Trellis Diagram 7 2.2 Viterbi Algorithm 9 2.2.1 Definition of Viterbi Algorithm 9 2.2.2 Viterbi Decoder 11 2.2.3 Example of a Viterbi Decoder 12 CHAPTER 3 TURBO CODE 15 3.1 Turbo Code Encoder 15 3.2 Turbo Code Decoding Algorithm: the MAP Algorithm 16 3.3 Turbo Code Decoder 20 CHAPTER 4 ARCHITECTURE OF DUAL MODE VITERBI/TURBO-CODE DECODER 23 4.1 Architecture Overview 23 4.2 Low Power Architecture Design 26 4.3 Sub-Module Architecture Design 31 CHAPTER 5 DUAL MODE VITERBI/TURBO-CODE DECODER IMPLEMENTATION 37 5.1 Implementation Design flow 37 5.2 Specification and Implementation Results 40 CHAPTER 6 CONCLUSION 47 REFERENCE 49 | |
| dc.language.iso | en | |
| dc.subject | 維特比 | zh_TW |
| dc.subject | 渦輪碼 | zh_TW |
| dc.subject | Turbo Code | en |
| dc.subject | Viterbi | en |
| dc.title | 雙模維特比及渦輪碼解碼器 | zh_TW |
| dc.title | Dual Mode Viterbi/Turbo-Code Decoder | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 闕志達,林伯星 | |
| dc.subject.keyword | 渦輪碼,維特比, | zh_TW |
| dc.subject.keyword | Turbo Code,Viterbi, | en |
| dc.relation.page | 50 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-12-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位: | 電子工程學研究所 | |
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| ntu-100-1.pdf 未授權公開取用 | 1.95 MB | Adobe PDF |
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