請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66453
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
dc.contributor.author | Chun-jen Wei | en |
dc.contributor.author | 魏君任 | zh_TW |
dc.date.accessioned | 2021-06-17T00:36:34Z | - |
dc.date.available | 2015-02-16 | |
dc.date.copyright | 2012-02-16 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-02-02 | |
dc.identifier.citation | [1] C. J. Wei, H. H. Chen, and S. J. Chen, “Design and Implementation of Block-Based Partitioning for Parallel Flip-Chip Power-Grid Analysis,” to be published by IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2012.
[2] Z. Zeng and P. Li, “Locality-Driven Parallel Power Grid Optimization,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 8, pp. 1190-1200, Aug. 2009. [3] E. Chiprout, “Fast Flip-chip Power Grid Analysis Via Locality and Grid Shells,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 485-488, Nov. 2004. [4] Y. Zhong and M. D. F. Wong, “Fast Block-Iterative Domain Decomposition Algorithm for IR Drop Analysis in Large Power Grid,” in Proc. 11th Symposium on Quality Electronic Design, pp. 277-283, March 2010. [5] M. Zhao, R. V. Panda, S. S. Sapatnekar, and D. Blaauw , “Hierarchical Analysis of Power Distribution Network,” IEEE Trans. Computer-aided Design of Integrated Circuits and Systems, vol. 21, no. 2, pp. 159-168, Feb. 2002. [6] C. W. Ho, A. E. Ruehli, and P. A. Brennan, “The Modified Nodal Approach to Network Analysis,” IEEE Trans. Circuits and Systems, vol. 22, no 6, pp. 504-509, Jun. 1975. [7] J. M. S. Silva, J. R. Phillips, and L. M. Silveira, “Efficient Simulation of Power Grids,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 10, pp. 1523-1532, Oct. 2010. [8] P. Li, “Power Grid Simulation via efficient Sampling-based Sensitivity Analysis and Hierarchical Symbolic Relaxation,” in Proc. ACM Design Automation Conference, pp. 664–669, June 2005. [9] H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Power Grid Analysis Using Random Walks,” IEEE Trans. Computer-aided Design of Integrated Circuits and Systems, vol. 24, no. 8, pp. 1204–1224, Aug. 2005. [10] J. N. Kozhaya, S. R. Nassif, and F. N. Najm, “A Multigrid-like Technique for Power Grid Analysis,” IEEE Trans. Computer-aided Design of Integrated Circuits and Systems, vol. 21, no. 10, pp. 1148–1160, Oct. 2002. [11] H. Su, E. Acar and S. R. Nassif, “Power Grid Reduction Based on Algebraic Multigrid Principles,” in Proc. ACM Design Automation Conference, pp. 109-112, June 2003. [12] Z. Zhu, B. Yao, and C.-K. Cheng, “Power Network analysis Using an Adaptive Algebraic Multigrid Approach,” in Proc. ACM Design Automation Conference, pp. 105–108, June 2003. [13] K. Sun, Q. Zhou, K. Mohanram, and D. C. Sorensen, “Parallel Domain Decomposition for Simulation of Large-scale Power Grids,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 54–59, Nov. 2007. [14] T.-H. Chen and C. C.-P. Chen, “Efficient Large-scale Power Grid Analysis Based on Preconditioned Krylov-subspace Iterative Methods,” in Proc. ACM Design Automation Conference, pp. 559–562, June 2001. [15] Z. Feng and P. Li, “Multigrid on GPU: Tackling Power Grid Analysis on Parallel SIMT Platforms,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 647-654, Nov. 2008. [16] H. H. Chen and J. S. Neely, “Interconnect and Circuit Modeling Techniques for Full-Chip Power Supply Noise Analysis,” IEEE Trans. Components, Packaging and Manufacturing Technology, vol. 21, no. 3, pp. 209-215, Aug. 1998. [17] S. Ekelof, “The Genesis of the Wheatstone Bridge,” IEEE Engineering Science and Education Journal, vol. 10, no. 1, pp. 37-40, Feb. 2001. [18] S. Kannan, M. Roberts, P. Mayes, D. Brelsford, and J. F. Skovira, “Workload Management with Loadleveler,” online available http://www.redbooks.ibm.com/pubs/pdfs/redbooks/sg246038.pdf [19] J. Janhunen, T. Pitkanen, O. Silven, and M. Juntti, “Fixed- and Floating-Point Processor Comparison for MIMO-OFDM Detector,” IEEE Journal Selected Topics in Signal Processing, vol. 5, no. 8, pp. 1588-1598, Dec. 2011. [20] T.-Y. Chen, Y.-. Lin, C.-F. Wu, C.-K. Wang, “Design and Analysis of Cost-Efficient IFFT FFT Processor Chip for Wireless OFDM Systems,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 760-763, Dec. 2010. [21] S.-Y. Peng, K.-T. Shr, C.-M. Chen, and Y-H Huang, “Energy-Efficient 128∼2048/1536-Point FFT Processor with Resource Block Mapping for 3GPP-LTE System,” in Proc. International Conference on Green Circuits and Systems (ICGCS), pp. 14-17, June 2010. [22] E. H. Wold and A. M. Despain, “Pipelined and Parallel-Pipeline FFT Processors for VLSI Implementations,” IEEE Trans. Computers, vol. 33, no. 5, pp. 414-426, May 1984. [23] C. Fang, R. Rutenbar, M. Püschel, and T. Chen, “Toward Efficient Static Analysis of Finite-Precision Effects in DSP Applications via Affine Arithmetic Modeling,” in Proc. ACM/IEEE Design Automation Conference, pp. 496–501, June 2003. [24] G. Constantinides and G. Woeginger, “The Complexity of Multiple Wordlength Assignment,” Applied Mathematics Letters, vol. 15, no. 2, pp. 137–140, 2002. [25] C. J. Wei, S. J. Chen, and Y.-H. Hu, “Effective Rounding Error Estimation for Fixed-point Implementation Arithmetic Units,” in Proc. Very Large Scale Integrated Circuits - Computer-aided Design Conference, pp. 463-466, 2009. [26] O. Sarbishei and K. Radecka, “Analysis of Mean-Square-Error (MSE) for Fixed-Point FFT Units”, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1732-1735, May 2011. [27] W. H. Chang, and T. Q. Nguyen, “On the Fixed-Point Accuracy Analysis of FFT Algorithms”, IEEE Trans. Signal Processing, vol. 56, no. 10, pp. 4673-4682, Oct. 2008. [28] C.-Y. Wang, C.-B. Kuo, and J.-Y. Jou, “Hybrid Word-Length Optimization Methods of Pipelined FFT Processors,” IEEE Trans. Computers, vol. 56, no. 8, pp. 1105-1118, Aug. 2007. [29] A. V. Oppenheim and R. W. Schafer, Digital Signal Processing, Prentice-Hall, New Jersey, 1975. [30] M. Willems, H. Keding, T. Grötket, and H. Meyr, “Fridge: An Interactive Fixed-point Code Generation Environment for HW/SW CoDesign,” in Proc. International Conference Acoustics, Speech, Signal Processing, pp. 287-290, Apr. 1997. [31] S. Kim, K. Kum, and W. Sung, “Fixed-Point Optimization Utility for C and C++ Based Digital Signal Processing Programs,” IEEE Trans. Circuits and Systems—II: Analog and Digital Signal Processing, vol. 45, no. 11, pp. 1455-1464, Nov. 1998. [32] K. Radecka and Z. Zilic, “Arithmetic Transforms for Compositions of Sequential and Imprecise Datapaths,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1382–1391, July 2006. [33] D.-U. Lee, A. A. Gaffar, R. C. Cheung, O. Mencer, W. Luk, and G. A. Constantinides, “Accuracy Guaranteed Bit-width Optimization,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 1990–2000, Oct. 2006. [34] E. Özer, A. P. Nisbet, and D. Gregg, “A Stochastic Bitwidth Estimation Technique for Compact and Low-power Custom Processors,” ACM Trans. Embedded Computing Systems (TECS), vol. 7, no. 3, pp. 34:1-30, Apr. 2008. [35] A. B. Kinsman and N. Nicolici, “Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no 3, pp. 405-413, March 2010. [36] Y.-Y. Chen, J.-Y. Jou, 'Bit Width Determination Using Complexity Information for OFDM system,' Thesis, National Chiao Tung University, Aug. 2008. [37] R. Durrett, Probability: Theory and Examples, Cambridge University Press, 2010. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66453 | - |
dc.description.abstract | 啟發式和近似演算法普遍用來解決實務上的問題,這類的方法允許某個程度的誤差因此而降低計算複雜度和計算時間。這設計準則經常的被使用無形中隱喻著用答案準確度來換取計算速度似乎是值得的。但實驗的結果卻顯示可經由增加演算的準確度來減少計算時間,於是,我們以兩個案例來探討。
第一個案例是在晶片電源網路分析時使用較精確的分割方式,該方法較高的準確度和可攜性使得網路分析系統得以使用最先進的多層平行技術。除了這個非算術性的方法之外,第二個案例描述了使用較精確的數學模型在定點數快速傅立葉轉換的設計和驗證上的效能增進。在這個案例中,我們首先導出高準確度的截捨誤差計算模型,然後根據給定的訊號-誤差比、用該模型計算定點數快速傅立葉轉換中每一個中間變數所需的小數位元數。其中,我們提出一個使用了全新概念的演算法,所有設計出的定點快速傅立葉轉換皆準確的符合訊號-截捨誤差比值的限制。 傳統上,當誤差是被容許的,解答就由較低準確度的計算來得知,然後再用些如搜尋的技術來得到更準確的解答。放鬆了準確度的限制使得計算較為容易、但也同時減低了整體效能。相較之下,使用我們為了追求最高準確度而研究出來的模型和方法、在較短的計算時間就可以得到更好的結果。實驗結果顯示緊縮在演算法發展過程的容許誤差將達成較好的效能。 | zh_TW |
dc.description.abstract | Heuristic and approximation algorithms are commonly used to solve real-world problems. Certain degree of error is allowed to lower the computation complexity and practical runtime. This implicitly becomes a design paradigm constantly used, which seems to be a worthy trade-off made between the accuracy and the runtime. However, experimental results show that we can decrease the runtime by increasing the accuracy of an algorithm. In this work, two cases are studied.
The first case is the analysis of power grid adopting an accurate partition scheme. The runtime is reduced with lower maximum memory usages. Higher accuracy and portability also make it adequate to work with other advanced parallel solvers as a multi-level parallel analyzing system for larger power grids. Beyond the above accurate non-arithmetic method, the second case describes the performance gain in using an accurate arithmetic model to aid the design and verification of fixed-point fast Fourier transforms. In this case, we first derive a model capable of computing the signal-to-quantization-noise ratio as accurate as that of simulating with ten thousand sets of input combinations. Then we arithmetically compute the necessary number of fractional bits of each variable in a fixed-point fast Fourier transform given a signal-to-quantization-noise ratio constraint. An algorithm facilitated by a novel idea is presented. All the resultant FFT designs accurately meet the constraint. Conventionally a solution is generated by inaccurate computations when error is allowed. Technologies such as search are used later for refinement. A loose constraint eases the computation but refinement afterward encumbers the performance. By contrast, our method and model are developed to achieve the highest accuracy and produce better results in a shorter runtime. The experimental results will show tightening the tolerance during algorithm development achieves better performance. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T00:36:34Z (GMT). No. of bitstreams: 1 ntu-101-D92921022-1.pdf: 4346574 bytes, checksum: a49b9a3f8b5ef4aaa134574507056805 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | CHAPTER 1. INTRODUCTION 1
CHAPTER 2. PRELIMINARY 5 2.1 Analysis of Power Grid 5 2.1.1 Conventional Analysis Methods and Flow 5 2.1.2 Parallel Processing of Analysis 13 2.2 Design of Fixed-point FFTs 17 2.2.1 Signal-to-Quantization-Noise Ratio 18 2.2.2 Necessary Number of Fractional Bits 19 2.2.3 Computation of SQNR 22 2.2.4 Conventional Model 23 CHAPTER 3. ANALYSIS OF POWER GRID FOR DESIGNS WITH HUNDREDS OF MILLIONS NODES 25 3.1 Concerns of Geometric Partition 25 3.1.1 Ideal Power Grid for Partitioning 25 3.1.2 Realistic Power-Grid Partitioning and Source of Errors 26 3.1.3 Error Reduction 30 3.1.4 Extension Size Determination 30 3.1.5 Portability 32 3.2 Proposed Parallel Analysis System 33 3.2.1 Area-based Partitioning versus Block-based Partitioning 34 3.2.2 Partitioning Procedure and Algorithm 35 3.2.3 Result Assembly 39 3.2.4 Computation Cost and Loading Balance 39 3.3 Experimental Results and Discussion 41 CHAPTER 4. ROUNDING ERROR COMPUTATION 55 4.1 Modeling and Computation 55 4.2 Accuracy and Time Complexity 62 CHAPTER 5. NECESSARY NUMBER OF FRACTIONAL BITS FOR FIXED-POINT FFTS 67 5.1 Weight of a Variable 67 5.2 Error Budget 69 5.3 Number of Fractional Bits Needed 70 5.4 Algorithm and Time Complexity 73 5.5 Experimental Results 74 CHAPTER 6. CONCLUSION AND FUTURE WORK 79 | |
dc.language.iso | en | |
dc.title | 應用於電源網路分析和快速傅立葉轉換之低誤差設計方法論 | zh_TW |
dc.title | Low Error Design Methodology for Power Grid Analysis and FFT | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-1 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 張耀文(Yao-Wen Chang),陳中平(Chung-Ping Chen),王廷基(Ting-Chi Wang),張克正(Keh-Jeng Chang),陳宏明(Hung-Ming Chen) | |
dc.subject.keyword | 電源網路,節點分析,聯立方程式,矩陣,平行處理,快速傅立葉轉換,四捨五入,截位,誤差,平均值,變異數,均方值,最佳化,位元寬,演算法,訊噪比, | zh_TW |
dc.subject.keyword | power grid,power distribution network,nodal analysis,matrix,system equations,LU decomposition,algebraic multigrid,partition,parallel processing,rounding error,mean,variance,mean square error,truncation,fast Fourier transform,DFT,FFT,optimization,bit width,word length,algorithm,variable weight,SQNR, | en |
dc.relation.page | 84 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-02-02 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-101-1.pdf 目前未授權公開取用 | 4.24 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。