利用超解析度技術之電視縮放控制器之演算法及硬體架構設計

Abstract

The goal of super resolution is to recover the high-resolution image with sharp edges and rich details from a low-resolution input image. Due to the increasing gap between the resolution of image sources and display devices, super resolution has become an essential technique in many applications. In this work, we focus on the application of TV scaler. Due to real-time requirement and low hardware-cost constraints, conventional TV scaler can only employ basic interpolation technique thus introduces some artifacts that degrade the viewing quality of the output sequences. Therefore, the goal of this work is to improve the performance of TV scaler by adopting the super resolution technique. The corresponded hardware design is also provided. We propose a low complexity super resolution algorithm which can provide vivid output image with rich details and sharp edges. There are two main contributions. First is the development of double interpolation up-sampling. Double interpolation quality evaluation can be used as a measurement of an interpolation operation. By using this double interpolation framework, the direction-adaptive upsampling algorithm is proposed to solve the zigzag artifact and enhance the quality of edges. The second contribution is the database-free texture synthesis technique. Based on the fractal property of nature images, it is possible to find proper high resolution patches in low resolution input image itself. Therefore, the texture synthesis can be performed without database to provide proper and rich details. The double interpolation framework for up-sampling and the reconstruction constraint for the final optimization combined with the texture synthesis form the whole super resolution algorithm. Experimental results show that the proposed super resolution algorithm performs better than other ones. For the VLSI hardware design, the target specification is set to 1920x1080 frame size, with throughput of 60 frames per second. The main contributions of hardware architecture design are one-pass double interpolation, tile-based gradient descent, and partial-sum reuse texture synthesis. One-pass double interpolation and tile-based gradient descent lower down the consumption of bandwidth and SRAM, while partial-sum reuse texture synthesis reduce 76 percent of the computational costs. The hardware is implemented with Verilog-HDL and synthesized with SYNOPSYS Design Compiler. TSMC 65nm cell library is adopted to design the hardware. The operation frequency is at 240MHz. The total gate count is 766K. We also verify the design with FPGA. The demo platform is based on Terasic DE4 development board with the Altera Stratix IV GX device. The FPGA demo system up-samples the video by the proposed super resolution hardware at the frame size of 1920x1080 and the frame rate of 24 frames per second. The results show that our architecture is able to provide high quality output in real-time while solving the problems of zigzag and blurred effects caused by conventional scaler.