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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 闕志達(Tzi-Dar Chiueh) | |
dc.contributor.author | Cheng-Hsiang Tsai | en |
dc.contributor.author | 蔡政祥 | zh_TW |
dc.date.accessioned | 2021-06-17T00:27:18Z | - |
dc.date.available | 2012-03-19 | |
dc.date.copyright | 2012-03-19 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-02-15 | |
dc.identifier.citation | [1] M.L. Liou and T.D. Chiueh, “A Low-Power Digital Matched Filter for Direct-Sequence Spread Spectrum Signal Acquisition,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 6, June 2001, pp. 933-943.
[2] P. C. Hsieh, J. S. Jhuang, P. Y. Tsai and T. D. Chiueh “A Low-Power Delay Buffer Using Gated Driver Tree,” IEEE Trans. on VLSI systems , Vol. 17, No. 9, Sept 2009 [3] N. Shibata, M. Watanabe, and Y. Tanabe, “A Current-Sensed High-Speed and Low-Power First-In–First-Out Memory Using a Wordline/Bitline-Swapped Dual-Port SRAM Cell,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 6, June 2002, pp. 375-350. [4] S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak and D.M. Sylvester, “Ultralow-voltage, minimum-energy CMOS,” IBM Journal of Research and Development, Vol.50, Issue:4.5 [5] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuit, Vol.24, No. 5, October 1989 [6] E. Seevinck, F. J. List and J. Lohstroh ,” Static-Noise Margin Analysis of MOS SRAM Cells” IEEE Journal of Solid-State Circuit, Vol. SC-22 No. 5 October 1987. [7] N.Verma and A.P. Chandrakasan , “A 256 kb 65nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundency,” IEEE Journal of Solid-State Circuit, Vol.43, No. 1, January 2008. [8] I. J. Chang, J. J. Kim, S. P. Park and K. Roy , “A 32kb 10T sub-threshold SRAM Array With Bit-interleaving and Differential Read Scheme in 90nm CMOS,” IEEE Journal of Solid-State Circuit, Vol. 44 No. 2 February 2009 [9] B. Zhai, S. Pant, L. Nazhadali, S. Hanson, J. Olson, A. Reeves, M. Minuth, R. Helfand, T. Austin, D. Sylvester and D. Blaauw, ”Energy-efficient subthreshold processor design,” IEEE Trans. VLSI. Syst., vol. 17, no. 8, pp. 1127-1137, August 2009 [10] I. J. Chang, J. J. Kim and K. Roy, ”Robust level converter design of sub-threshold logic,” in Proc. ISLPED, 2006, pp. 14-19. [11] J. Kulkarni , K. Kim and K. Roy , “A 160mV Robust Schmitt Trigger Based Sub-threshold SRAM,” IEEE Journal of Solid-State Circuit, Vol. 42 pp.2303-2313, Oct. 2007 [12] B. H. Calhoun and A.P. Chandrakasan , “A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation,” IEEE Journal of Solid-State Circuit, Vol.42, No. 3, March 2007 [13] C. H. Lo and S.Y. Huang , “P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation,” IEEE Journal of Solid-State Circuit, Vol.46, No. 3, March 2011 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66251 | - |
dc.description.abstract | 在這篇論文裡,我們提出了一種可以操作在超低電壓的延遲緩衝器,我們捨棄了常見由隨機存取記憶體(SRAM)組成的架構,而是根據我們所需要的功能,採用了環狀計數型態的緩衝器架構(ring counter based delay buffer),我們以環狀計數器(ring counter)來當作位址指定器,來降低動態功率(dynamic power)的消耗,而資料儲存的部分,我們使用了10T的架構,這比傳統的6T架構的memory cell更適合工作在超低電壓(次臨界區域-sub-threshold region),進而整個延遲緩衝器可以比傳統的設計更為省電。
為了降低動態功耗,我們在延遲緩衝器中的環狀計數器採用閘式時脈架構,我們充分的利用延遲緩衝器的特性,因此可以預先知道那些部份的電路沒有被使用到,那麼我們就會關閉當時沒有使用到的閘式時脈驅動器以及環狀計數器,來減少不必要的能量消耗。同樣的觀念也可以使用在輸入端與輸出端的驅動器,來降低整體的動態功率。 我們為了讓延遲緩衝器能夠工作在低電壓,因此我們使用的記憶晶胞(memory cell)是10顆電晶體的架構,我們把讀取跟寫入的路徑分開,以避免讀取時造成資料翻轉的錯誤。除此使用10T外,我們還使用了虛擬的電源跟虛擬的地(virtual VDD & virtual ground)來幫助記憶裝置的讀取跟寫入。除此之外,我們使用了穿插式的讀取資料線(interleaved read bit line)來避免讀取時間的變異(time variation)造成的讀取錯誤。而在資料輸入的與輸出的驅動器,我們修改了原本常見的三態反向器,根據他們的需求,各自更換了適合的電路,讓輸入端更快更省電,而輸出端在低電壓更為穩定。藉由上面提到的架構,我們完成了一個可以操作在0.2V的延遲緩衝器,比傳統1V的版本,耗電量可以降低了許多,其中漏電流更降低了約99%。 | zh_TW |
dc.description.abstract | In this thesis, we propose a delay buffer which can be operated in ultra low voltage. Unlike the conventional structure which is SRAM based delay buffer. According to the function we need, we choose ring counter based delay buffer instead. We use ring counter as an address pointer. By this method, we can reduce the dynamic power. About memory cell part, we choose 10T memory cell. It is more suitable than conventional 6T memory cell in operating in subtheshold region. Therefore, the delay buffer can save a lot of power than conventional design.
In order to reduce dynamic power consumption , we use gated clock structure in the ring counter. We adequately use the characteristic of delay buffer. We can know that which part will not be used in advanced. Therefore, we will disable the clock gated tree and part of ring counter that we don't use. It can reduce the redundant power consumption. Also, we can apply this idea to the input and output driver to reduce the dynamic power of delay buffer. In order to make delay buffer operate in ultra low voltage, so the memory cell type we use is 10T. We can separate the path we read and write. It can avoid the data flipping when we read the stored data. Besides 10T cell type, we also apply virtual VDD and virtual ground methods to help write data into the cell and read data from the cell. Besides, we use bitline interleaving structure to avoid read failure that caused by time variation. In input and output driver tree, we modify the conventional tristate inverter. According to the requirement, we replace them with a suitable version. In input driver tree, we make it faster and lower power. In the output driver, we can operate in even more stable in low voltage than conventional tristate inverter. By the method we mentioned above, we implement a delay buffer which can be operate in 0.2 voltage. Compare with conventional 1 voltage version, the power consumption is reduced, and the leakage power reduce about 99%. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T00:27:18Z (GMT). No. of bitstreams: 1 ntu-101-R98943048-1.pdf: 1778283 bytes, checksum: 7368ea848ee554145a059b9a33546a31 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 1. 第一章 緒論 1
1.1 研究動機 1 1.2 論文組織介紹 2 2. 第二章 延遲緩衝器架構 3 2.1 常用的延遲緩衝器 3 2.1.1. 移位式暫存器 3 2.1.2. 記憶體合成的延遲緩衝器 4 2.2 環狀計數器型延遲緩衝器架構 5 2.2.1. 環狀計數器 5 2.2.2. 環狀計數器架構的延遲緩衝器 6 2.3 閘式時脈環狀計數器 7 2.3.1. 多餘的時脈能量消耗 7 2.3.2. 閘式時脈的架構 8 3. 第三章 樹狀閘式延遲緩衝器架構 10 3.1 樹狀閘式環狀計數器 10 3.1.1. C-element的使用 10 3.1.2. 樹狀閘式時脈驅動器 11 3.2 樹狀閘式輸入驅動器 14 3.3 樹狀閘式輸出驅動器 17 4. 第四章 超低電壓延遲緩衝器電路設計 19 4.1 低電壓電路特性 20 4.1.1. 漏電流分析 21 4.1.2. 電路穩定性分析 23 4.2 低漏電二相位樹狀閘式環狀計數器 25 4.2.1. 二相位時脈訊號 25 4.2.2. 閘式電源電路設計(Power Gating) 27 4.3 記憶裝置電路設計 29 4.3.1. 傳統6T記憶晶胞 29 4.3.2. 8T記憶晶胞 31 4.3.3. 10T記憶晶胞 32 4.3.4. 基本記憶裝置區塊 35 4.3.5. 新型記憶區塊電路設計 37 4.4 新型樹狀閘式輸入與輸出驅動器 39 4.4.1. 新型低電壓的輸入端三態反向器 40 4.4.2. 新型低電壓的輸出端三態反向器 42 4.5 模擬結果 44 4.5.1. 不同電壓效能模擬 44 4.5.2. 穩定性模擬結果 48 5. 第五章 新型數位邏輯位準轉換器電路設計 50 5.1 數位邏輯位準轉換器的使用 50 5.2 新型輸出端數位邏輯位準轉換器電路設計 51 6. 第六章 電路佈局圖與佈局後模擬結果 56 6.1 基本電路佈局 56 6.2 延遲緩衝器電路佈局設計 57 6.3 佈局後模擬結果與量測考量 61 7. 第七章 結論與展望 63 8. 參考文獻 66 | |
dc.language.iso | zh-TW | |
dc.title | 超低電壓低漏電延遲緩衝器電路設計 | zh_TW |
dc.title | Ultra Low Voltage And Low Leakage Delay Buffer Circuit Design | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),蔡佩芸(Pei-Yun Tsai) | |
dc.subject.keyword | 延遲緩衝器,環狀計數器,記憶晶胞,超低電壓,次臨界區域,低耗電,低漏電, | zh_TW |
dc.subject.keyword | delay buffer,ring counter,memory cell,ultra low voltage,subthreshold region,low power,low leakage, | en |
dc.relation.page | 67 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-02-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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