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標題: | 針對當代混合尺寸電路設計之解析擺置 Analytical Placement for Modern Mixed-Size Circuit Designs |
作者: | Meng-Kai Hsu 徐孟楷 |
指導教授: | 張耀文(Yao-Wen Chang) |
關鍵字: | 實體設計,擺置,巨集元件擺置,可繞度,三維積體電路, Physical Design,Placement,Macro Placement,Routability,3D ICs, |
出版年 : | 2012 |
學位: | 博士 |
摘要: | 隨著製程的演進,超大型積體電路設計的複雜度也急遽上升。近年來,單一積體電路晶片所包含之電晶體已達到數十億以上。為了對抗此急速高升的設計複雜度,重複利用嵌入式記憶體、類比電路、矽智產等已設計好之巨集元件已成為趨勢。除此之外,亦有使用三維積體電路技術來克服現代化高複雜度設計的挑戰。然而,相較於標準元件的大小,巨集元件以及在三維積體電路技術中所使用之直通矽晶穿孔通常會佔用較大之晶片面積,使得電路的擺置問題更為複雜。尤其,由於巨集元件或直通矽晶穿孔本身通常會佔用部分繞線金屬層,除了造成繞線資源之減少外,將使得考慮可繞度之設計問題更加困難。一個電路如果繞線失敗,即使擁有較佳之時序、功率及效能等,也將無法成功量產。因此,在當代混合尺寸電路設計中,考慮巨集元件擺置、可繞度以及三維積體電路整合等關鍵課題之擺置方法將愈來愈為重要。
在這份論文中,我們針對上述當代混合尺寸電路設計中所面臨之關鍵課題提出了數個全新的擺置演算法。這份論文首先介紹我們的解析擺置基礎,有別於過去的研究,我們的全域擺置是基於一種全新的穩定加權平均線長模型以及一種多層密度架構以提升解析擺置演算法的效能。接著,我們提出一個針對混合尺寸電路設計、使用旋轉力的統一解析擺置方法。相較於過去傳統的解析擺置方法中,只使用了由線長以及密度所造成的力來推動欲擺置的元件到達其最佳位置,我們建立了旋轉力的模型來旋轉較大的巨集元件,並有效率地在線長方面做更進一步的改善。然而,由於現今電路擺置所使用之線長模型與實際繞線仍具有顯著的差異,因此在電路的實體設計中,除了線長之外,考慮繞線成功率的擺置方法亦愈來愈重要。不同於先前的研究大多利用剩餘空間的分配或是擴大元件尺寸來減少繞線擁擠區域,我們以S形(sigmoid)函數為基礎,提出繞線溢出非線性最佳化演算法來提升繞線成功率。此外,我們亦提出一個繞線擁擠區域非線性最佳化演算法來減少繞線擁擠區域並同時降低總繞線長度。最後,針對新興三維積體電路設計,我們提出一個考慮直通矽晶穿孔大小和位置的三維積體電路擺置流程架構,除了文獻上的直通矽晶穿孔總個數最佳化之外,我們所提出的全域擺置演算法亦有效地考慮直通矽晶穿孔所引起的密度問題,除了可以得到最佳直通矽晶穿孔總個數以及總矽晶片面積,更可以提升三維積體電路設計之可繞度以及總繞線長度。 With the advance of process technology, billions of transistors (or millions of standard cells) can be integrated into a single chip. To facilitate the design complexity, pre-designed macros are often reused, such as embedded memories, analog blocks, intellectual property (IP) modules, etc. Moreover, the three-dimensional integrated circuit (3D IC) technology also emerged to overcome the challenges in interconnect and integration complexity in modern circuit designs. While pre-designed macros usually have areas much larger than those of standard cells, through-silicon vias (TSVs) required for transmitting signals among different dies for the 3D IC technology also occupy more significant silicon areas than standard cells. As a result, a modern circuit design may contain a large number of big blocks and standard cells with various sizes. The great difference between big blocks and small standard cells has incurred significant challenges to modern mixed-size placement. Especially, since pre-designed macros or TSVs usually occupy several metal layers by themselves, these big blocks also bring up significant challenges to circuit routability. Therefore, it is of particular importance to develop effective placement techniques considering the critical issues in modern mixed-size circuit designs including macro placement, routability, and 3D IC integration. In this dissertation, we propose several novel placement algorithms to consider the aforementioned critical issues. The dissertation first starts with our analytical placement basics which are based on a novel stable weighted-average wirelength model and a new multi-layer sigmoid potential model. Then, we present a unified analytical global placement algorithm based on a novel rotation force to resolve the intrinsic limitations with macro handling for analytical placement. To cope with the significant mismatch between existing wirelength models and the congestion objective in placement, and the macro porosity problem (several metal layers are usually occupied by big macros), we present a novel routability-driven analytical placement algorithm for large-scale mixed-size circuit designs by introducing a novel sigmoid function based overflow optimization method and a new net congestion optimization method for analytical placement. For the emerging 3D IC technology, we propose a 3D IC analytical placement algorithm which considers the sizes of TSVs and the physical positions for TSV insertion during placement. Experimental results show the effectiveness and efficiency of our proposed algorithms. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65644 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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