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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林茂昭(Mao-Chao Lin) | |
| dc.contributor.author | Bo-Wen Tung | en |
| dc.contributor.author | 童柏文 | zh_TW |
| dc.date.accessioned | 2021-06-16T23:54:55Z | - |
| dc.date.available | 2012-07-20 | |
| dc.date.copyright | 2012-07-20 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-07-19 | |
| dc.identifier.citation | [1] C.-L. Wey, M.-D. Shieh, and S.-Y. Lin, “Algorithm of finding the first two minimum values and their hardware implementation,” IEEE Trans. Circuits and Systems, vol. 55, pp. 3430–3437, Dec. 2008.
[2] M. Karkooti, P. Radosavljevic, and J. R. Cavallaro, “Configurable, high throughput, irregular LDPC decoder architecture: Tradeoff analysis and implementation,” IEEE ASAP ’06, pp. 360–367, Sep. 2006. [3] R. Gallager, “Low-density parity-check codes,” IRE Trans. Inf. Theory, vol. 8, pp. 21–28, Jan. 1962. [4] D. J. C. MacKay, “Good error correcting codes based on very sparse matrices,” IEEE Trans. Inf. Theory, vol. 45, pp. 399–431, Mar. 1999. [5] V. D. Kolesnik, “Probability decoding of majority codes,” Prob. Peredachi Inform., vol. 7, pp. 3–12, Jul. 1971. 66 [6] Y. Kou, S. Lin, and M. Fossorier, “Low density parity check codes based on finite geometries: A rediscovery and more,” IEEE Trans. Inform. Theory, vol. 47, pp. 2711–2736, Nov. 2001. [7] M. Fossorier, M. Mihaljevic, and H. Imai, “Reduced complexity iterative decoding of low-density parity check codes based on belief propagation,” IEEE Trans. Commun., vol. 47, pp. 673–680, May 1999. [8] J. Chen and M. Fossorier, “Near optimum universal belief propagation based decoding of low-density parity check codes,” IEEE Trans. Commun., vol. 50, pp. 406–414, Mar. 2002. [9] J. Chen and M. Fossorier, “Density evolution for two improved BP-based decoding algorithms of LDPC codes,” IEEE Trans. Letters, vol. 6, pp. 208–210, May 2002. [10] P. Radosavljevic, A. Baynast, de, and J. R. Cavallaro, “Optimized message passing schedules for LDPC decoding,” Asilomar Conf. on Signals, Sys. and Computers (IEEE), pp. 591–595, Oct. 2005. [11] J. Zhang and M. Fossorier, “Shuffled belief propagation decoding,” Asilomar Conf. on Signals, Sys. and Computers (IEEE), vol. 1, pp. 8–15, Nov. 2002. [12] M. Mansour and N. Shanbhag, “High-throughput LDPC decoders,” IEEE Trans. Very Large Scale Integration Systems, vol. 11, pp. 976–996, Dec. 2003. [13] D. E. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” Signal Proc. Systems SIPS 2004. IEEE Workshop on, pp. 107–112, Oct. 2004. [14] J. Zhang, , and M. Fossorier, “Shuffled iterative decoding,” IEEE Trans. Commun., vol. 53, pp. 209–213, Feb. 2005. [15] M. Mansour and N. Shanbhag, “Turbo decoder architectures for low-density parity-check codes,” GLOBECOM ’02. IEEE, vol. 2, pp. 1383–1388, Nov. 2002. [16] T. Mohsenin, D. N. Truong, and B. M. Baas, “A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders,” IEEE Trans. Circuits and Systems, vol. 57, pp. 1048–1061, May 2010. [17] S. Lin and D. J. Costello, Jr., Error Control Coding. Pearson Prentice Hall, 2nd ed., 2004. [18] R. M. Tanner, “A recursive approach to low complexity codes,” IEEE Trans. Inf. Theory, vol. IT-27, pp. 533–547, Sep. 1981. [19] M. Fossorier, “Quasi-cyclic low-density parity-check codes from circulant permutation matrices,” IEEE Trans. Inf. Theory, vol. 50, pp. 1788–1793, Aug. 2004. [20] IEEE-802.11n, “Wireless LAN medium access control and physical layer specifications: Enhancements for higher throughput,” P802.11n/D11.0, Jun. 2009. [21] T. Richardson and R. Urbanke, “Efficient encoding of low-density parity-check codes,” IEEE Trans. Inf. Theory, vol. 47, pp. 638–656, Feb. 2001. [22] A. L. LIN and A. J. BLANKSBY, “Permuted accelerated LDPC (low density parity check) decoder.” Patent Application, 02 2010. US 2010/0031119 A1. [23] T. Mohsenin and B. M. Baas, “Split-row: A reduced complexity, high throughput LDPC decoder architecture,” Proc. ICCD, pp. 320–325, 2006. [24] E. Liao, E. Yeo, and B. Nikolic, “Low-density parity-check code constructions for hardware implementation,” IEEE Int’l Conf. Commun., vol. 5, pp. 2573–2577, Jun. 2004. [25] A. Darabiha, A. C. Carusone, and F. R. Kschischang, “Multi-gbit/sec low density parity check decoders with reduced interconnect complexity,” IEEE ISCAS 2005, pp. 5194–5197, 2005. [26] T. Mohsenin, D. N. Truong, and B. M. Baas, “A thresholding algorithm for improved split-row decoding of LDPC codes,” Asilomar Conf. on Signals, Sys. and Computers (IEEE), pp. 448–451, Nov. 2008. [27] T. Mohsenin, D. N. Truong, and B. M. Baas, “A improved split-row threshold decoding algorithm for LDPC codes,” Proc. IEEE ICC, pp. 1–5, Jun. 2009. [28] E. Amador, R. Pacalet, and V. Rezard, “Optimum LDPC decoder: A memory architecture problem,” DAC ’09. 46th ACM/IEEE, pp. 891–896, Jul. 2009. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65629 | - |
| dc.description.abstract | 現今的LDPC 解碼器在實作上所面對的其中一個主要的挑戰乃在於，隨著平行處理單元的增加，其內部的連線複雜度亦隨之上升，進而使得晶片整體的面積、延遲以及功耗跟著增加。在此篇論文中，為了能獲得由Mosehnin 提出的split-row threshold algorithm 對硬體所帶來的好處，以及保留住802.11n 標準中所定義的LDPC碼的優異糾錯能力，我們提出了一個採用縮減量化法的分核架構。而實作的結果顯示，在繞線階段前的面積相近的情況下，採用我們所提出之架構的解碼器的面積為2.58平方公厘，並且可達到85%的利用率，而採用傳統未分割的架構的解碼器其利用率僅達70%，面積則為3平方公厘。 | zh_TW |
| dc.description.abstract | One of the main challenges of implementing an LDPC code decoder is that the interconnection
complexity is growing along with the number of the parallel processing units, which results in the increased delay, power dissipation, and chip area. In this thesis, we propose a design called split-core architecture with reduced-quantization method which reserves the benefit of split-row threshold algorithm proposed by Mohsenin and simultaneously retains the good error performance for a multi-mode LDPC decoder of 802.11n standard. The implementation results show that the area of a decoder with our proposed architecture is 2.58 mm2 with a final core utilization of 85%, as compared to the area of 3 mm2 and a core utilization of 70% for the non-splitting architecture, while the area sizes are similar for both architectures before the routing process. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T23:54:55Z (GMT). No. of bitstreams: 1 ntu-101-R99942109-1.pdf: 1953955 bytes, checksum: cd9f28a24a0961541cad66f25923e109 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 1 Introduction 1
2 Low-Density Parity-Check Codes 4 2.1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 LDPC Codes in 802.11n . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Encoding Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3.1 Richardson-Urbanke Algorithm . . . . . . . . . . . . . . . . . 9 2.4 Decoding Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4.1 Sum-Product Algorithm . . . . . . . . . . . . . . . . . . . . . 11 2.4.2 Min-Sum Algorithm . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.3 Improved Min-Sum Algorithm . . . . . . . . . . . . . . . . . . 17 2.5 Efficient decoding schedules . . . . . . . . . . . . . . . . . . . . . . . 19 2.5.1 Two-Phase Message Passing . . . . . . . . . . . . . . . . . . . 20 2.5.2 Shuffled Decoding . . . . . . . . . . . . . . . . . . . . . . . . . 20 i 2.5.3 Layered Decoding . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5.4 Permuted Accelerated Decoding . . . . . . . . . . . . . . . . . 25 3 Analysis of Split-Row Threshold Algorithm using on LDPC Codes of 802.11n 29 3.1 Routing Congestion Issue . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2 Split-Row Threshold Algorithm . . . . . . . . . . . . . . . . . . . . . 31 3.3 Analysis of Performance for LDPC Codes of 802.11n . . . . . . . . . 36 4 Proposed Split-Core Architecture and Circuit Implementation 40 4.1 Proposed Split-Core Architecture . . . . . . . . . . . . . . . . . . . . 41 4.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.1 APP Memory Design . . . . . . . . . . . . . . . . . . . . . . . 45 4.2.2 Extrinsic Messages Memory . . . . . . . . . . . . . . . . . . . 49 4.2.3 Check Node Processor . . . . . . . . . . . . . . . . . . . . . . 51 4.2.4 Early Termination Strategy . . . . . . . . . . . . . . . . . . . 54 4.2.5 Main Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.4 Implementation Results . . . . . . . . . . . . . . . . . . . . . . . . . 61 5 Conclusions 64 Bibliography 66 ii A Parity Check Matrices in 802.11n 71 iii | |
| dc.language.iso | en | |
| dc.subject | 降低繞線壅塞 | zh_TW |
| dc.subject | 分割列-臨界演算法 | zh_TW |
| dc.subject | 排列式加速解碼 | zh_TW |
| dc.subject | 最小和演算法 | zh_TW |
| dc.subject | 802.11n | zh_TW |
| dc.subject | 低密度同位檢查碼 | zh_TW |
| dc.subject | routing congestion reduction | en |
| dc.subject | 802.11n | en |
| dc.subject | min-sum algorithm | en |
| dc.subject | permuted accelerated decoding | en |
| dc.subject | split-row threshold algorithm | en |
| dc.subject | low-density parity check code | en |
| dc.title | 使用於IEEE 802.11n規範中之低密度同位檢查碼解碼器硬體架構設計 | zh_TW |
| dc.title | A Hardware Architecture Design of the Low-Density Parity-Check Code Decoder for IEEE 802.11n Standard | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蘇賜麟(Szu-Lin Su),蘇育德(Yu-Ted Su),趙啟超(Chi-chao Chao),呂忠津(Chung-Chin Lu) | |
| dc.subject.keyword | 低密度同位檢查碼,802.11n,最小和演算法,排列式加速解碼,分割列-臨界演算法,降低繞線壅塞, | zh_TW |
| dc.subject.keyword | low-density parity check code,802.11n,min-sum algorithm,permuted accelerated decoding,split-row threshold algorithm,routing congestion reduction, | en |
| dc.relation.page | 74 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-07-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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