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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 黃鐘揚(Chung-Yang Huang) | |
dc.contributor.author | Yu-Fan Yin | en |
dc.contributor.author | 尹煜帆 | zh_TW |
dc.date.accessioned | 2021-06-16T23:46:22Z | - |
dc.date.available | 2012-08-01 | |
dc.date.copyright | 2012-08-01 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-07-23 | |
dc.identifier.citation | [1] P. Rashinkar, P. Paterson, and L. Singh, System-on-a-Chip Verification: Methodology and Techniques. Boston, MA: Kluwer, 2000.
[2] M. Abramovici, P. R. Menon, and D. T. Miller, “Critical path tracing: An alternative to fault simulation,” in Proc DAC, 1983, pp. 214-220. [3] M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design. Rockville, MD: Computer Science, 1990. [4] S.-Y. Huang, “A fading algorithm for sequential fault diagnosis,” in Proc. DFT VLSI Syst., 2004, pp. 139-147. [5] A. Smith, A. Veneris, M. F. Ali, and A. Viglas, “Fault diagnosis and logic debugging using Boolean satisfiability,” in IEEE Trans. Computer-Aided Design, vol. 24, no. 10, pp. 1606-1621, Oct. 2005. [6] A. Veneris and I. N. Hajj, “Design error diagnosis and correction via test vector simulation,” in IEEE Trans. on CAD, vol. 18, no. 12, pp. 1803–1816, 1999. [7] Y. Chen, S. Safarpour, Joao M.-S., and A. Veneris, “Automated design debugging with maximum satisfiability,” in IEEE Trans. Computer-Aided Design, vol. 29, no. 11, pp. 1804-1817, Nov. 2010. [8] S. Safarpour, and A. Veneris, “Automated design debugging with abstraction and refinement,” in IEEE Trans. Computer-Aided Design, vol. 28, no. 10, pp. 1597-1608, Oct. 2009. [9] B. Keng, and A. Veneris, “Managing complexity in design debugging with sequential abstraction and refinement,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference, 2010. [10] B. Keng, S. Safarpour, and A. Veneris, “Bounded model debugging,” in IEEE Trans. Computer-Aided Design, vol. 29, no.11, pp. 1790-1803, Nov. 2010. [11] B. Keng, and A. Veneris, “Scaling VLSI design debugging with interpolation,” in Formal Methods in CAD, 2009. [12] H. Mangassarian, A. Veneris, D. E. Smith, and S. Safarpour, “Debugging with dominance: on-the-fly debug solution implications,” in IEEE /ACM Int’l Conference on Computer-Aided Design (ICCAD), 2011. [13] H.-H. Yeh, C.-Y. Wu, and C.-Y. (Ric) Huang, “QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification,” in International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), 2012. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65492 | - |
dc.description.abstract | 功能性驗證可以對於一個有錯誤的設計,找出一條錯誤軌跡,其中包含了設計的規格與實作之間的不一致處。而自動化設計除錯可以利用這條錯誤軌跡,找出可能導致此錯誤的根源。這方面過去已經有許多能快速處理大型設計與長軌跡的研究,但是所找出的錯誤根源品質卻仍然不足,造成設計者要用人工的方式從幾百到幾千個可能的錯誤根源中,找出真正的錯誤根源。這篇論文提出了一個二級的除錯架構來減少誤認的錯誤根源。第一級使用了傳統的除錯演算法找出初始的錯誤根源。在第二級中,我們利用注入錯誤、狀態選擇,以及使每次找到的錯誤傳送路徑有所不同等技術,來產生替代的測試輸入。然後替代的測試輸入會被驗證並用來產生新的錯誤軌跡。利用此軌跡除錯後,如果有錯誤根源不在原本的可能的錯誤根源及新得到的可能的錯誤根源的交集中,那這些被誤認的錯誤根源即可被移除。實驗結果顯示我們所提出的演算法可以減少超過75%可能的錯誤根源,顯示出此方法用於改善設計除錯技術的可行性。 | zh_TW |
dc.description.abstract | Given an erroneous design, functional verification returns an error trace containing a mismatch between the specification and the implementation of a design. Automated design debugging utilizes this error trace to identify candidates causing the error. There are remarkable debugging works in handling large designs and long error traces. However, the quality of error candidates remains poor, and it’s hard for designers to locate the actual error source among hundreds or thousands of candidates. This thesis proposes a two-stage debugging framework that reduces error candidate number. The first stage performs conventional debugging algorithm to get initial error candidates. In the second stage, alternative test sequences are generated by error injection, state selection, and error propagation path differentiation techniques. Then, the alternative test sequences are validated to produce alternative error traces. After debugging, redundant candidates can be removed if they are not in the intersection of the original candidate set and the new candidate set. Experimental results show that the proposed algorithm is able to reduce more than 75% error candidates, which demonstrates the viability of this approach in improving design debugging techniques. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T23:46:22Z (GMT). No. of bitstreams: 1 ntu-101-R99943089-1.pdf: 852301 bytes, checksum: b7ca2e68fce3345a209a550e68b86f17 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 誌謝 i
中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES vii Chapter 1 Introduction 1 1.1 Debugging Problem 2 1.1.1 Definition of Debugging Problem 2 1.1.2 Development of SAT-based Debugging Techniques 3 1.2 Problem Formulation 6 1.3 Related Work 9 1.4 Contribution 14 1.5 Thesis Organization 14 Chapter 2 Debugging Framework 15 2.1 Conventional Debugging Framework 15 2.2 Proposed Two-stage Debugging Framework 16 2.2.1 Functional Debugging 16 2.2.2 Alternative Test Sequence Generation 17 2.2.3 Test Sequence Validation 17 2.2.4 Candidate Dropping 17 Chapter 3 Error Candidate Reduction 18 3.1 Observation 18 3.2 Error Injection 21 3.3 State Selection 22 3.4 Propagation Path Differentiation 23 3.5 Acceleration 24 3.5.1 Cardinality Constraint Relaxation 24 3.5.2 Error Candidate Grouping 25 3.6 Overall Algorithm 26 3.7 Extended to Multi-Error Debugging 27 Chapter 4 Experiments 29 4.1 Experiment Description 29 4.2 Experimental Results 30 4.2.1 Removing MUX 30 4.2.2 Without Propagation Path Differentiation 31 4.2.3 With Propagation Path Differentiation 32 4.2.4 Comparison 33 4.2.5 Overall Result 34 Chapter 5 Conclusions and Future Work 36 REFERENCE 37 | |
dc.language.iso | en | |
dc.title | 減少自動化設計除錯中誤認的錯誤根源 | zh_TW |
dc.title | Error Candidate Reduction in Automated Design Debugging | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃俊達(Juinn-Dar Huang),江介宏(Jie-Hong Jiang),顏嘉志(Chia-Chih Yen) | |
dc.subject.keyword | 除錯,診斷,驗證, | zh_TW |
dc.subject.keyword | debugging,diagnosis,verification, | en |
dc.relation.page | 38 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-07-24 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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