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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65489完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚(Chung-Yang (Ric) | |
| dc.contributor.author | Po-Kai Huang | en |
| dc.contributor.author | 黃柏凱 | zh_TW |
| dc.date.accessioned | 2021-06-16T23:46:10Z | - |
| dc.date.available | 2014-08-03 | |
| dc.date.copyright | 2012-08-03 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-07-23 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65489 | - |
| dc.description.abstract | 對於現場可程式化邏輯陣列的設計來說，即時性部分修改的技術在這幾年來逐漸成為重要的需求。利用這項技術，我們可以只修改部分系統，並同時保留系統其餘的部分來改變其行為。而這對需要有彈性與及時適應硬體架構的軍事與通訊設備而言，此技術顯得特別有效。然而，現今產生符合部分修正的適當修改之設計工具，仍只有受限的支援與自動化。此外，對於使用者來說，當修改的數量相當多時，利用手動來取得要求的功能是不切實際且沒有效率的。在這篇論文中，我們提出一個有效的自動化流程在系統中找尋需要考慮的部分，並產生符合修正的適當修改。精確地來說，我們的演算法可只藉由重新更改某些找查表（Look-Up Table）的功能，並保持原先的單元繞線與擺放，來實現所需要的功能。此外，我們開發若干技巧來降低修正流程的複雜度，並改善其效能。實驗結果顯示，我們的演算法可以在邏輯階層與暫存器轉移階層中，實現不同目標的功能。 | zh_TW |
| dc.description.abstract | On-the-fly partial reconfiguration on FPGA designs has become an increasingly im-portant requirement in recent years. With this attribute, the behavior of a system can be changed partially while the rest of the design is still preserved. It is especially useful for applications in such as military or communication devices which require flexible and adaptive hardware. However, there are limited supports and automation in design tools to generate appropriate modifications for partial reconfiguration. Moreover, when there are significant numbers of modifications, it is impractical and inefficient for users to derive the desired functions in a manual way. In this thesis, we propose an efficient automated flow which is able to search for the portions of the device needed for consideration and generate proper modifications for the reconfiguration. To be precise, our algorithm achieves the desired functionalities by only reconfiguring some of the Look-Up Tables (LUTs) while preserving engineering efforts on cell interconnections and placement. In addition, we develop several techniques to alleviate the complexity and improve the performance of the reconfiguration process. The experimental results show that our algorithm can achieve the reconfiguration of various targeted functions in both the logic and Register-Transfer (RT) levels efficiently and effectively. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T23:46:10Z (GMT). No. of bitstreams: 1 ntu-101-R99921026-1.pdf: 788325 bytes, checksum: 389a6f50d8a73d134f4e1230e1e4f799 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES vii Chapter 1 Introduction 1 1.1 Introduction to On-the-fly FPGA Reconfiguration 1 1.2 Contributions of this Thesis 4 1.3 Organization of this Thesis 5 Chapter 2 Preliminaries 6 2.1 Terminologies 6 2.2 Error Diagnosis 12 2.2.1 Simulation-based Diagnosis 12 2.2.2 Symbolic Diagnosis 14 2.2.3 SAT-based Diagnosis 15 2.2.4 Summary 17 2.3 Error Rectification 18 2.3.1 Error-modeling Rectification 18 2.3.2 Structural Rectification 18 2.3.3 Formal-based Resynthesis Rectification 19 2.3.4 Summary 20 2.3.5 Problem Definition 21 Chapter 3 Diagnosis for FPGA Reconfiguration 22 3.1 Simulation-based Diagnosis 22 3.1.1 Simulation-based Algorithm 22 3.1.2 Ranking Metrics 24 3.2 SAT-based Diagnosis 28 3.2.1 SAT-based Algorithm 28 3.2.2 Candidate Ranking by Conflict Analysis 33 3.2.3 Candidate Ranking by Single Restriction 36 3.3 Integrated Simulation & SAT-based Diagnosis 38 Chapter 4 Rectification for FPGA Reconfiguration 40 4.1 Algorithm Overview 40 4.2 Rectification with Counterexample-based Learning 43 4.2.1 Counterexample-based Learning 44 4.3 Incremental Rectification by Partial-fix Configuration 46 Chapter 5 Experimental Results 50 5.1 Results under Different Types of Functional Changes 50 5.1.1 Results of Gate-level Design Changes 51 5.1.2 Results of RTL Design Changes 52 5.2 Results under Different Strategies 55 5.2.1 The Effectiveness of Incremental Rectification 55 5.2.2 The Efficiency of Counterexample Learning 56 5.2.3 The Effectiveness of SAT-based Candidate Ranking 57 Chapter 6 Conclusions and Future Work 59 REFERENCE 60 | |
| dc.language.iso | en | |
| dc.title | 利用以滿足性解法器為基礎的高效邏輯修正技術來達成即時性可修正的現場可程式化邏輯陣列應用 | zh_TW |
| dc.title | Toward On-the-fly Reconfigurable FPGA Applications by Efficient SAT-Based Logic Rectification Techniques | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 王俊堯(Chun-Yao Wang),顏嘉志(Chia-Chih Yen),江蕙如(Hui-Ru Jiang) | |
| dc.subject.keyword | 錯誤診斷,邏輯修正,布林可滿足性,現場可程式化邏輯陣列, | zh_TW |
| dc.subject.keyword | Error diagnosis,Logic rectification,Boolean satisfiability,FPGA, | en |
| dc.relation.page | 64 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-07-24 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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