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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65478完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 汪重光(Chorng-Kuang Wang) | |
| dc.contributor.author | Yi-Long Yu | en |
| dc.contributor.author | 尤乙龍 | zh_TW |
| dc.date.accessioned | 2021-06-16T23:45:29Z | - |
| dc.date.available | 2017-07-27 | |
| dc.date.copyright | 2012-07-27 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-07-24 | |
| dc.identifier.citation | [2.1] Jeffrey Fredenburg, Michael Flynn “A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-Shaping SAR ADC” ISSCC Dig. Tech. papers, pp.468-470, Feb. 2012.
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[2.6] Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon “A 1.36μW Adaptive CMOS Image Sensor with Reconfigurable Modes of Operation From Available Energy/Illumination for Distributed Wireless Sensor Network” ISSCC Dig. Tech. papers, pp.112-113, Feb. 2012. [2.7] Nick Van Helleputte, Sunyoung Kim, Hyejung Kim, Jong Pal Kim Chris Van Hoof1, Refet Firat Yazicioglu1 “A 160μA Biopotential Acquisition ASIC with Fully Integrated IA and Motion-Artifact Suppression” ISSCC Dig. Tech. papers, pp.118-119, Feb. 2012. [2.8] Jerald Yoo1, Long Yan, Dina El-Damak, Muhammad Bin Altaf, Ali Shoeb, Hoi-Jun Yoo, Anantha Chandrakasan “An 8-Channel Scalable EEG Acquisition SoC with Fully Integrated Patient-Specific Seizure Classification and Recording Processor” ISSCC Dig. Tech. papers, pp.292-293, Feb. 2012. [2.9] Shuenn-Yuh Lee, Y-C. Su, M-C. Liang, J-H. Hong, C-H. Hsieh, C-M. Yang, Y-Y. Chen, H-Y. Lai, J-W. Lin, Q. Fang, “A Programmable Implantable Micro-Stimulator SoC with Wireless Telemetry: Application in Closed-Loop Endocardial Stimulation for cardiac Pacemaker” ISSCC Dig. Tech. papers, pp.44-45, Feb. 2011. [2.10] Rikky Muller, Simone Gambini, Jan M. Rabaey “A 0.013mm2 5μW DC-Coupled Neural Signal Acquisition IC with 0.5V Supply” ISSCC Dig. Tech. papers, pp.302-303, Feb. 2011. [2.11] Alan Wong, Mark Dawkins, Gabriele Devita, Nick Kasparidis, Andreas Katsiamis, Oliver King, Franco Lauria, Johannes Schiff, Alison Burdett “A 1V 5mA Multimode IEEE 802.15.6/Bluetooth ow-Energy WBAN Transceiver for Bi-otelemetry Aplications” ISSCC Dig. Tech. papers, pp.300-301, Feb. 2012 [3.1] Behzad Razavi and Bruce A. Wooley, “Design Techniques for High-speed, High-Resolution Comparators”, IEEE J. Solid-state Circuits, vol. 27, no. 12, pp. 1916-1926. Dec. 1992 [3.2] You-Kuang Chang, Chao-Shiun Wang and Chorng-Kuang Wang, “ A 8-bit 500-KS/s Low Power SAR ADC for Bio-Medical Applications”, Asian Solid-State Circuits Conference (A-SSCC) Dig. Tech. Papers, pp. 228-231, Nov. 2007. [3.3] Wen-Yi Pang, Chao-Shiun Wang, You-Kuang Chang, Nai-Kuan Chou, and Chorng-Kuang Wang, “ A 10-bit 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical Applications”, Asian Solid-State Circuits Conference (A-SSCC) Dig. Tech. Papers, pp. 149-152, Nov. 2009. [3.4] Yasuhide Kuramochi, Akira Matsuzawa, Masayuki Kawbata, “ A 0.05-mm2 110-μW 10-b Self-Calibration Successive Approximation ADC Core in 0.18-μm CMOS”, Asian Solid-State Circuits Conference (A-SSCC) Dig. Tech. Papers, pp. 224-227, Nov. 2007. [3.5] Erkan Alpman, Hasnain Lakdawala, L. Richard Carley, K. Soumyanath, “ A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS” ISSCC Dig. Tech. papers, pp.76-77,77a, Feb. 2009. [3.6] Robert H. Walden, “Analog-to-Digital Converter Survey and Analysis” IEEE J. Solid-State Circuits, vol. 17, no. 4, pp.539-550, Apr. 1999. [3.7] Jeffrey A. Fredenburg and Michael P. Flynn “Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch” IEEE Trans. Circuit Syst. I, vol. 59, no.99, pp 1-13, Jan. 2012 [3.8] Wei Xiong, Yang Guo, Ute Zschieschang, Hagen Klauk, and Boris Murmann, “A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass” IEEE J. Solid-State Circuits, vol. 45, no. 7, pp.1380-1388, Jul. 2010 [4.1] Michael D. Scott, Bernhard E. Boser, and Kristofer S. J. Pister, “An Ul-tralow-Energy ADC for Smart Dust” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp.1123-1129, Jul. 2003 [4.2] van Elzakker, M., van Tuijl, E., Geraedts, P., Schinkel, D., Klumperink, E., Nauta,B.,“A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC” ISSCC Dig. Tech. papers, pp.244-245, Feb. 2008. [4.3] Jing Yang ; Naing, T.L. ; Brodersen, B. ; “A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS” in Custom Integrated Circuits Conference (CICC) Dig. Tech. Papers, pp. 287-290, Sept. 2009. [4.4] Yang, H.Y., Sarpeshkar, R., “A Bio-Inspired Ultra-Energy-Efficient Ana-log-to-Digital Converter for Biomedical Applications” IEEE Trans. Circuit Syst. I, vol. 53, no.11, pp 2349-2356, Nov. 2006. [4.5] Wenbo Liu, Pingli Huang, Yun Chiu “A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC Achieving Over 90dB SFDR” ISSCC Dig. Tech. papers, pp.380-381, Feb. 2010. [4.6] Naveen Verma, Anantha P. Chandrakasan “A 25μW 100kS/s 12b ADC for Wire-less Micro-Sensor Applications” ISSCC Dig. Tech. papers, pp.82-83, Feb. 2006. [4.7] Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, “A 10b 50MS/s 820μW SAR ADC with On-Chip Digital Calibration” ISSCC Dig. Tech. papers, pp.384-385, Feb. 2010. [4.8] Chun C. Lee, and Michael P. Flynn, “A 12b 50MS/s 3.5mW SAR assisted 2-stage pipeline ADC” in Symp. VLSI Circuits Dig. Tech. papers, pp. 239-240, Jun. 2010 [4.9] Shuo-Wei Michael Chen and Robert W. Brodersen, “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-μm CMOS” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp.2669-2680, Dec. 2006 [4.10] Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, and Franco Maloberti, “A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp.1111-1121, Jun. 2010 [4.11] Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang and Chun-Cheng Liu “A 0.9-V 11-bit 25-MS/s Binary-Search SAR ADC in 90-nm CMOS”, Asian Solid-State Circuits Conference (A-SSCC) Dig. Tech. Papers, pp. 69-72, Nov. 2011. [4.12] B. Murmann, “ADC Performance Survey 1997-2012” [Online]. Available: http://www.standford.edu/~murmann/adcsurvey.html [4.13] Geert Van der Plas and Bob Verbruggen “A 150 MS/s 133 μW 7 bit ADC in 90 nm Digital CMOS” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.2631-2640, Dec. 2008 [4.14] Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto Sangiovanni-Vincentelli, Jan Craninckx and Geert Van der Plas, “A 6-bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS” in Symp. VLSI Circuits Dig. Tech. papers, pp. 238-239, Jun. 2009 [4.15] Behzad Razavi “Design of Sample-and-Hold Amplifiers for High-speed Low-Voltage A/D Converters” in Custom Integrated Circuits Conference (CICC) Dig. Tech. Papers, pp. 59-66, Sept. 1997. [4.16] Brian P. Ginsburg, and Anantha P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp.739-747, Apr. 2007 [4.17] Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu and Soon-Jyh Chang, “A 9-bit 150-MS/s 1.53-mW Subranged SAR ADC in 90-nm CMOS” in Symp. VLSI Circuits Dig. Tech. papers, pp. 243-244, Jun. 2010 [4.18] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, and Ying-Zu Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp.731-740, Apr. 2010 [4.19] Chun C. Lee, and Michael P. Flynn, “A SAR-Assisted Two-Stage Pipeline ADC” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp.859-869, Apr. 2011 [4.20] Masanori Furuta, Mai Nozawa, and Tetsuro Itakura, “A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique” IEEE J. Solid-State Circuits, vol. 46, no. 6, pp.1360-1370, Jun. 2011 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65478 | - |
| dc.description.abstract | 本論文致力研究於適合生醫應用，有效利用能量之類比數位轉換器，並且提出製作於一百八十奈米製程之互補式金屬氧化半導體的逼近暫取器型類比數位轉換器使用主動-被動數位類比轉換器技巧。而量測之結果可以證實此技巧確實達到將低能量消耗的效果。
主動-被動數位類比轉換器技巧是使用一個附增的主動數位類比轉換器但只增加百分之五的面積，如此可以有效的防止因為在傳統型電容陣列中，重複的充電與放電在相同電容中所造成的能量浪費尤其是在較大的位元中的浪費。而運作的方式共分為四個步驟：取樣、主動數位類比轉換器工作、位元傳送和被動數位類比轉換器工作。而主動數位類比轉換器的最佳化位元數目與能量消耗都有被分析與經過模擬的驗證。 測試版適合生技應用的使用主動-被動數位類比轉換器逼近暫取器型類比數位轉換器達到十位元的解析度工作於五十萬赫茲的取樣頻率使用一伏的供給電壓。在符合不匹配現象下電容陣列中減少的能量比例是百分之九十三相較於傳統型的電容陣列。核心面積是零點一五毫米平方並且與傳統式的電容陣列相較下也減少了百分之七十五的面積。再量測的結果上達到了訊雜扭曲比五十九點二分貝，相當於九點六位元的等效位元數，整體功率消耗也因主動-被動數位類比轉換器技巧而有顯著的減少，總消耗功率為二十八微瓦質量指標為七十七費焦耳每轉換步驟。整體而言本論文提供一減少電容陣列能量消耗的技巧，並且由實做的晶片得到此技巧功能的驗證。 | zh_TW |
| dc.description.abstract | This thesis researches an energy-efficient analog to digital converter (ADC) for bio-medical applications, and proposes a master-slave digital to analog converter (M-S DAC) technique implemented in a successive approximation register analog (SAR) ADC chip fabricated in 180nm CMOS. The function of energy-reduction is demonstrated by the measurements of the chip.
The M-S DAC technique using an additional master DAC (MDAC) with extra area of 5% in capacitor array can prevent energy from waste in vain, which is caused by the repeatedly charge and discharge in the same capacitor of conventional capacitor array, particularly in larger bits. The sequences of M-S DAC are sampling, MDAC cycling, bit transferring, slave DAC (SDAC) cycling. The optimum number of bits and energy dis-sipation in the capacitor array is analyzed and identified by the simulation and meas-urements. The prototype SAR ADC using the M-S DAC has the resolution of 10-bit, sam-pling rate at 500KS per second with supply voltage of 1V which is adopted by bio-applications in common. The reduction ratio of energy dissipation in capacitor array is 93% in this work within the mismatch constraint and the core area is 0.15 mm2 with the area-reduction of 75% in capacitor array compared with conventional array. This prototype achieves the signal-to-noise-and-distortion-ratio of 59.2dB in equivalent to effective number of bits of 9.6-bit in measurement. The power consumption significantly reduces by M-S DAC technique. The total power is 28μW and it reaches the FoM 77fJ/Conversion-step. Conclusively, this thesis provides a technique for capacitor array to reduce energy dissipation, and demonstrated the function of the technique by a fabri-cated chip. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T23:45:29Z (GMT). No. of bitstreams: 1 ntu-101-R98943139-1.pdf: 2741751 bytes, checksum: 8c16d6cfe6283892b47dd773fdb18095 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 ii Abstract iii Contents v List of Figures vii List of Tables xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Challenges in Design of Biomedical Signal Detector 2 1.3 Transmitter and Receiver for Bio-Medical Applications 3 1.4 Introduction of Analog to Digital Converter for Bio-Medical Applications 4 1.5 Thesis Overview 5 Chapter 2 Analog to Digital Converters for Bio-Applications 6 2.1 Introduction 6 2.2 Characteristics of ADCs for Bio-Applications 7 2.2.1 Bio-Sensors 8 2.2.2 Image Detector 10 2.2.3 Bio-Potential 11 2.2.4 Low Power Transceivers 13 2.3 Summary of ADCs for Bio-Applications 14 Chapter 3 Analysis of Mismatch in Capacitor Array 16 3.1 Introduction 16 3.2 Analysis of INL and SNDR 17 3.3 Topologies of Capacitor Array 18 3.3.1 Binary-Weighted Capacitor Array 19 3.3.2 Series Split-DAC Capacitor Array 20 3.3.3 C-2C Capacitor Array 22 3.4 Analyzed and Simulated Results of Mismatch 24 Chapter 4 Design and Implementation of Low Power SAR ADC 33 4.1 Introduction 33 4.2 Architecture of Conventional SAR ADC 35 4.2.1 Basics of SAR ADC 36 4.2.2 Sample and Hold Circuit 37 4.2.3 Offset-Cancelling Comparator 39 4.2.4 Successive Approximation Registers Logic 40 4.3 Proposed Master-Slave DAC Technique 41 4.3.1 Energy Dissipation in Capacitor Array 42 4.3.2 Proposed Master-Slave Technique 48 4.4 Circuit Design and Implementation 58 4.4.1 Architecture of M-S DAC SAR ADC 59 4.4.2 Capacitor array 61 4.4.3 Sampling switches 64 4.4.4 Comparators 68 4.4.5 SAR Logic 71 4.5 Simulated Results 72 4.6 Measured Results 75 Chapter 5 Conclusions 82 Appendix A Bibliography 84 | |
| dc.language.iso | en | |
| dc.title | 於應用生醫系統之低功率類比數位轉換器 | zh_TW |
| dc.title | Low Power Analog to Digital Converter for Bio-Medical Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵,吳介琮,郭泰豪,黃柏鈞 | |
| dc.subject.keyword | 生醫應用,低功率,逐次逼近暫取器型類比數位轉換器,主動-被動數位類比轉換器,不匹配,電容陣列, | zh_TW |
| dc.subject.keyword | bio-application,low power,low voltage,SAR ADC,energy-efficient,M-S DAC,mismatched capacitor array, | en |
| dc.relation.page | 92 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-07-24 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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