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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平 | |
dc.contributor.author | Shang-Yu Shieh | en |
dc.contributor.author | 謝尚祐 | zh_TW |
dc.date.accessioned | 2021-06-16T23:26:19Z | - |
dc.date.available | 2017-08-01 | |
dc.date.copyright | 2012-08-01 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-07-31 | |
dc.identifier.citation | [1] Yung-Hsin Lin, Kuo-Lin Zheng, and Ke-Horng Chen, “Power MOSFET Array for Smooth Pole Tracking in LDO Regulator Compensation,” in Proc. IEEE Midwest Symp. Circuits and Systems (MWSCAS), pp. 554-557, 2007.
[2] Huan-JenYang, Han-Hsiang Huang, Chi-Lin Chen, Ming-Hsin Huang, and Ke-Horng Chen, “Current Feedback Compensation (CFC) Technique for Adaptively Adjusting the Phase Margin in Capacitor-Free LDO Regulators,” in Proc. IEEE Midwest Symp. Circuits and Systems (MWSCAS), pp, 5-8, 2008. [3] Chia-Hsiang Lin, Ke-Horng Chen, and Hong-Wei Huang, “Low-Dropout Regulators with Adaptive Reference Control and Dynamic Push-Pull Techniques for Enhancing Transient Performance,” IEEE Trans. Power Electron, vol. 24,no. 4, pp. 1016-1022, Apr. 2009 [4] M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732-1742, Aug. 2007. [5] P. Favrat, P. Deval and M. J. Declercq, ”A high-efficiency CMOS voltage doubler,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, Mar. 1998. [6] Starzyk, J.A, Ying-Wei Jan and Fengjing Qiu, “A DC-DC charge pump design based on voltage doublers,” IEEE Trans. Circuits Syst-I, Fundamental theory and Applications, vol. 48, no. 3, pp. 350-359, Mar. 2001. [7] Chun-Yu Hsieh, Po-Chin Fan and Ke-Horng Chen, “A Dual Phase Charge Pump with Compact Size,” in Proc. IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.202-205, 2007. [8] Yean-Kuo Luo, Ke-Horng Chen, and Wei-Chou Hsu, “A Dual-Phase Charge Pump Regulator with Nano-Ampere Switched-Capacitor CMOS Voltage Reference for Achieving Low Output Ripples,” in Proc. IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 446-449, 2008. [9] R. B. Ridley, “A new, continuous-time model for current-mode control,” IEEE Trans. Power Electron., vol. 6, pp. 271-280, April 1991. [10] Cheung Fai Lee, Philip K. T. “A Monolithic Current-Mode CMOS DC-DC Converter with On-Chip Current-Sensing Technique,”. IEEE J. Solid-State Circuits. vol. 39, pp.3-13, Jan. 2004. [11] Feng-Fei Ma, Wei-Zen Chen, and Jiin-Chuan Wu, “A Monolithic Current-Mode Buck Converter With Advanced Control and Protection Circuits,” IEEE Transaction on Power Electronics, pp, 1836-1846, Sept. 2007. [12] Ke-Horng Chen, Hong-Wei Huang, and Sy-Yen Kuo, “Fast-Transient DC-DC Converter with On-Chip Compensated Error Amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 12, pp. 1150-1154, Dec. 2007. [13] Wu, P.Y, Tsui, S.Y.S, Mok, P.K.T, “Area- and Power-Efficient Monolithic Buck Converters With Pseudo-Type III Compensation,” IEEE Journal of Solid-State Circuits. Vol. 45, Issue: 8, pp.1446-1455, Aug. 2010 [14] B. Razavi, Design of Analog CMOS Integrated Circuit, McGraw-Hill Higher Education, 2001. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65129 | - |
dc.description.abstract | 在消費性電子產品中,尤以手持式產品的應用上,需求越來越廣泛。擁有高效能與小型化的電源轉換器日趨重要。為了有效使用有限的電池能量,電源管理系統為晶片系統中非常重要的一環。切換式電源轉換器因其高效率而被廣泛地運用於電源管理模組中。然而,切換式電源轉換器通常需要外部電感以及電容。更甚者,由於系統穩定性的因素,還需要外部補償電容以及電阻作為系統補償之用。因此,如何縮小電源模組的面積,同時又能兼顧高效能的電源轉換器,將是一個重要的課題。
本論文所提出的內容,是利用輸出波型為主,磁滯直流轉直流降壓轉換器,主要訴求在改善一般磁滯的輸出波型大小,接此達到穩壓的效果.除此之外,擁有好的抽載變化之效果.甚至,在補償方面也捨棄傳統的PI補償方式,捨棄外部的補償原件,改用一個P 補償的方式來移除外部補償電容的使用。然而,因為採用不同的補償方式,在負載調節(Load Regulation)的表現勢必要有所補償。因此,電桿電流動態調整機制在此論文提出,用來改善負載調節表現,來實現一個不需任何補償元件,負載調節表現良好的電源管理晶片。整個實驗結果會在第五章呈現。 | zh_TW |
dc.description.abstract | In recent years, portable devices involve several integrated chips with different functionality into the same printed-circuit-board (PCB) for achieving various functions. It needs a highly integrated power management module to reduce the volume and weight in order to keep up with the trend of compact size. Unfortunately, the off-chip inductor and capacitors for the high-efficiency switch-mode DC-DC converters occupy the large PCB area. That results in the extra manufacture cost and the problem for system-on-a-chip (SoC) integration. In other words, a highly integrated power management module is necessary for achieving high performance and small footprint area in today’s power management design.
This paper proposes a ripple based technique hysteresis buck converter, this circuit have better regulation and fast transient response than before. Furthermore, this circuit uses the P compensator to remove the use of the compensation capacitor instead of the conventional PI compensator . However, owing to the change of the compensation method, the load regulation performance should be compensated. Thus, the dynamic dc current scaling is proposed in this paper to enhancement the load regulation performance. In the ch5, the whole measurement results are presented. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T23:26:19Z (GMT). No. of bitstreams: 1 ntu-101-R99943164-1.pdf: 1256149 bytes, checksum: b79372b064b9787f5be4d4a06d458280 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 誌 謝 i
摘 要 ii ABSTRACT iii Contents iv Chapter 1 1 Introduction 1 1.1 Background of Regulators 1 1.2 Classification of Voltage Regulators 2 1.2.1 Linear Regulators 2 1.2.2 Switching Capacitor Circuits 4 1.2.3 Switching Regulators 5 1.3 Design Motivation 9 1.4 Thesis Organization 13 Chapter 2 14 The Small-Signal Analysis in Ripple Based Current mode Buck converter 14 2.1 Basic operation of Hysteresis buck converter 14 2.2 Simple Model of the Hysteresis current mode Buck converter 15 2.3 Small Signal Model of the proposed Ripple based technique 18 2.4 The loop gain analysis with P compensator for stability of the system 22 Chapter 3 24 The Proposed Ripple Based Technique 24 3.1 The proposed ripple based current mode hysteresis buck converter 25 3.2 Modulation method at transient response 27 3.3 Dynamic dc current ripple scaling 28 Chapter 4 30 The Circuit Implementation 30 4.1 Current Sense circuit 30 4.2 Fixed Hysteretic Current Window Circuit 32 4.3 The Hysteresis Window generator and Dynamic dc current ripple scaling 34 4.4 The zero current detect (ZCD) and non-overlap 36 Chapter 5 37 Whole chip experimental Results 37 Chapter 6 45 Conclusion 45 6.1 Future Work 45 REFERENCES 47 | |
dc.language.iso | en | |
dc.title | 以輸出波形為基準磁滯控制之直流-直流降壓轉換器 | zh_TW |
dc.title | Ripple Based Hysteresis Buck Converter | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳秋麟,陳科宏 | |
dc.subject.keyword | 直流-直流 降壓,磁滯,快速暫態響應, | zh_TW |
dc.subject.keyword | DC-DC Buck,Hysteresis,Fast transient, | en |
dc.relation.page | 48 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-07-31 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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