針對三維積體電路中穿矽通孔所造成之微小延遲錯誤之測試技術

Abstract

穿矽通孔(Through silicon via, TSV)是一種廣泛被使用的三維積體電路連線，本篇論文提出發生缺陷的TSV會導致放置於周圍的邏輯閘發生微小延遲錯誤。我們考慮的缺陷有TSV造成之物理上的壓力以及TSV絕緣層上的破洞，並對受到這兩種缺陷所影響之邏輯閘進行模擬，證明TSV引起之微小錯誤(TSV-induced small delay fault, TSDF)的存在。對TSV引起之微小錯誤我們提出了一套新的測試技術，此技術首先由電路布局中萃取出受到容易受到TSV缺陷影響的邏輯閘，接下來對萃取出的錯誤清單進行時間感知之自動測試圖樣產生。值得一提的是本技術不需要額外的可測試性電路設計，也不需要直接用探針去測試TSV，這是與以往的技術很大的不同之處。我們的實驗結果展示此技術可以提升測試覆蓋率上述兩種缺陷引起之微小錯誤將近43%以及20%，另外對於測試圖樣的額外長度增長低於5%。

Through silicon via (TSV) is a widely used interconnect technology in three dimensional integrated circuits (3D ICs). This paper shows that defective TSVs can induce small delay faults in surrounding logic gates. We present simulation results of TSV-induced small delay fault (TSDF) due to mechanical stress or pinhole leakage. A test technique is proposed to detect TSDF using a physical-aware fault extractor and timing-aware ATPG. This technique requires no DfT area overhead and no direct TSV probing. Experimental results on benchmark circuits show that test coverage can be improved by nearly 43% and 20% for stress-induced and leakage-induced TSDF, respectively. In our results, the test length overheads of both TSDF are less than 5%.