矽穿孔技術與鰭式場效應電晶體應力源之應力分析

Abstract

IC 上可容納的電晶體數目，約每隔18 個月便會增加一倍，性能也將提升一 倍，為了遵循摩爾定律，過去的方式是將電晶體的尺寸不停的縮小，然而在22 nm節點以下由於曝光顯影的問題，製程變得相當的困難，取而代之的方法主要有從結構上改變成三維結構，例如鰭式場效應電晶體，又或者是將封裝的方式改成三維堆疊，例如矽穿孔技術，如此以來便可以在相同的面積上，增加更多的效能。 矽穿孔技術利用金屬將孔洞填滿以達到傳遞訊號的功能，由於金屬和半導體 材料的熱膨脹係數相差很大，導致製程完後回到常溫會產生相當大的應變，此應 變會改變電晶體的特性使元件缺乏一致性而難以控制甚至會破壞元件。 在本論文中，我們將計算由矽穿孔技術所造成的應變，進而分析它對於週遭 電晶體的影響。我們一開始先利用二維的模型定義keep-out zone，發現孔洞排成圓形的方式會減低keep-out zone 的大小，如此可以使晶圓上放入更多的電晶體。接著為了符合真實的情況，我們由Kane-Mindlin 的理論成功得到三維情況下應變分佈的解析解，因為我們的解析解只適用於晶圓的中間平面，但元件一般是在晶圓的表面，所以我們必須乘上一個常數去修正，我們將商業套裝軟體的結果與解析解進行比較，發現誤差非常的小，另外我們也用重疊原理考慮多個矽穿孔技術所造成的應力分佈，經由一些修正，我們也可以得到相當接近的結果。最後我們再進一步的考慮如果材料是非各向等性會和我們在假設各向等性下得到的解析解有多少的誤差，經由修正後，結果也非常的好。 90 nm 節點時所使用的應力源應變技術也可以用在未來的三維電晶體上，本 論文的另一部份將談到三維鰭式場效應電晶體應力源的應力分析，一開始我們先 回顧文獻裡適用於傳統平面電晶體，由差排對通道施加應力的解析解，接著我們 利用商業套裝軟體對於鰭式場效應電晶體將源汲極換成矽鍺施加應力作一個尺 寸最佳化，之後我們還比較了一種將源汲極包住後對通道施加應力的方法，最後 我們發現將源汲極包住的方法不只少了一道蝕刻的製程，在尺寸最佳化後它對通 道造成的應力也會大於將源汲極直接換成矽鍺的方法。

The numbers of transistor in the circuit and performance may be double every eighteen months. To follow Moore’s law, we scaled down the transistor in the past,but the lithography technology beyond 22nm node may suffer from bottleneck. There are some technologies to solve this problem, one is three dimension structure likes FinFET, and another is three dimension package likes TSVs. The via may be filled with metal to connect the signal. Because of the large difference of coefficient of thermal expansion between metal and semiconductor, it will lead to strain field as the process temperature is cooling down to room temperature. The strain may change the uniformity or deform the device. In this thesis, we will calculate the strain field induced by TSVs and check the effect to surrounding device. At first, we use two dimensions model to define the keep-out zone and we find the circular pattern can put more transistors because it will decrease the keep-out zone. To compare with the real situation, we derive the analytic solution in three dimensions by the Kane-Mindlin theory. Our model is fit for the middle plane of wafer and the device will often locate in the surface of wafer, so we need to revise it by correction factor. We find the result is similar between numeric solution and analytic solution. Besides, we use the superposition theory to fit the strain field of multiple TSVs, we get the similar result by corrections. At last,we further compare isotropic material of analytic solution with orthotropic material of numeric solution. We can still get the similar result by corrections. The strain technology used in the 90 nm node can still be well suited to the three dimensions transistor. The other part of this thesis will introduce the strain analysis of FinFET stressor. Firstly, we study the strain analytic solution of edge dislocation used in the planar structure which enhances the device performance. Secondly, we optimize the size of replaced S/D SiGe stressor by commercial tool. Afterward we simulate the wrapped stressor and find the wrapped stressor with two advantages. One is the etching process is less and the other is the strain field in the channel is higher than replaced stressor as the size optimization.