請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64826完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳宗霖(Tzong-Lin Wu) | |
| dc.contributor.author | Yu-Jen Cheng | en |
| dc.contributor.author | 鄭余任 | zh_TW |
| dc.date.accessioned | 2021-06-16T23:00:33Z | - |
| dc.date.available | 2013-08-17 | |
| dc.date.copyright | 2012-08-17 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-07 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64826 | - |
| dc.description.abstract | 在運用各種耦合傳輸線的高速差動信號傳輸系統中，維持差模信號的傳輸品質以及有效地抑制共模雜訊是確保接收端具有良好信號完整度的決定性因素。為此，我們提出了一個結合共模濾波器效果的新式被動等化器，其除了能夠等化差模信號外亦能過濾共模雜訊，名為「VCPW-R」。所提出之等化器可製作於封裝或印刷電路基板上，其具有價格低廉、體積小以及適用於不同傳輸速率之優點。
本論文將會先介紹幾種常見的耦合傳輸線，之後再描述所提出結構(即VCPW-R)的整體架構與相應的等效電路模型。此結構於差模及共模的傳輸特性分別利用奇模和偶模半電路進行分析。此外，我們也對此結構提出一個兼顧差模與共模傳輸特性之共設計流程，利用此設計流程針對8 Gb/s差動傳輸找出一組設計參數並用於實作測試電路板。根據實作板的頻域及時域量測結果，所提出結構之差模等化及共模濾波效果成功地獲得驗證。 | zh_TW |
| dc.description.abstract | In high-speed differential signal transmission using various kinds of coupled lines, good signal integrity (SI) at the receiving end is mainly attributed to high quality of the transmitted differential-mode signal and effective suppression of the generated common-mode noise. In view of this, an innovative passive equalizer able to not only equalize differential-mode signals but also filter common-mode noise, named “VCPW-R”, is proposed so that the two modes can be well treated with a low cost, compact and adaptable structure on a package or PCB substrate.
After the discussion of the characteristic of typical coupled lines, the configuration and corresponding equivalent model of the proposed VCPW-R is described. The characteristics of the proposed structure under differential-mode and common-mode transmission are discussed separately with the corresponding half-circuit models. Based on the proposed co-design flow, which takes both modes into consideration, a set of the design parameters are determined for 8 Gb/s differential transmission and utilized in the fabrication of test boards. The frequency-domain and time-domain measurements of the test board successfully demonstrate the effectiveness of the proposed structure. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T23:00:33Z (GMT). No. of bitstreams: 1 ntu-101-R99942014-1.pdf: 2487283 bytes, checksum: c9f3a4bb48aecca643777e4ce2bd84a2 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
中文摘要 i ABSTRACT ii CONTENTS iii LIST OF FIGURES v LIST OF TABLES viii ACRONYMS ix Chapter1 Introduction 1 1.1 Research Motivation 1 1.2 Literature Review 2 1.3 Proposed Research and Thesis Outline 3 Chapter2 Fundamentals of Coupled Microstrip Lines and Coupled Slotlines 6 2.1 Configuration of Typical Coupled Lines 6 2.2 Coupled Microstrip Lines 8 2.2.1 Fundamental Modes and Odd/Even-Mode Technique 8 2.2.2 Electromagnetic Characteristics 12 2.3 Coupled Slotlines 18 2.3.1 Fundamental Modes and Odd/Even-Mode Technique 18 2.3.2 Electromagnetic Characteristics 22 Chapter3 Differential Lines over Proposed Via-Conducted Coplanar Waveguide with Resistive Load (VCPW-R) 25 3.1 Physical Configuration 25 3.2 Equivalent Circuit Model 27 3.3 Half Circuit Analysis 33 3.3.1 Odd-Mode Half Circuit Model 33 3.3.2 Even-Mode Half Circuit Model 38 Chapter4 Design and Optimization for VCPW-R 41 4.1 Design for Differential-Mode Equalization 41 4.1.1 Step Response of Transmission-Line Systems with VCPW-R 41 4.1.2 Optimization of Equalization Effect 48 4.1.3 Design Examples and Validation 50 4.2 Design for Common-Mode Filtering 55 4.2.1 Formula for Common-Mode Insertion Loss Scc21 55 4.2.2 Design Concept 58 4.3 Co-Design Consideration 59 Chapter5 Applications of Proposed VCPW-R: A Case Study 62 5.1 Overview on Test Samples and Measuring Instruments 62 5.2 Frequency-Domain Validation 66 5.3 Time-Domain Validation 69 Chapter 6 Conclusion 72 REFERENCE 74 PUBLICATION LIST 81 | |
| dc.language.iso | en | |
| dc.subject | 頻率相依損耗 | zh_TW |
| dc.subject | 信號完整度 | zh_TW |
| dc.subject | 共模抑制 | zh_TW |
| dc.subject | 耦合線 | zh_TW |
| dc.subject | 等化 | zh_TW |
| dc.subject | 差模等化器 | zh_TW |
| dc.subject | 高速差動傳輸 | zh_TW |
| dc.subject | high-speed differential transmission | en |
| dc.subject | Common-mode suppression | en |
| dc.subject | coupled lines | en |
| dc.subject | differential-mode equalizer | en |
| dc.subject | equalization | en |
| dc.subject | frequency-dependent loss | en |
| dc.subject | signal integrity | en |
| dc.title | 一用於兆赫層級差動信號傳輸兼具寬頻共模濾波特性之新穎差模等化器 | zh_TW |
| dc.title | A Novel Differential-Mode Equalizer with Broadband Common-Mode Filtering for Gbps Differential Signaling | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成,邱奕鵬,盧信嘉,邱政男 | |
| dc.subject.keyword | 共模抑制,耦合線,差模等化器,等化,頻率相依損耗,高速差動傳輸,信號完整度, | zh_TW |
| dc.subject.keyword | Common-mode suppression,coupled lines,differential-mode equalizer,equalization,frequency-dependent loss,high-speed differential transmission,signal integrity, | en |
| dc.relation.page | 81 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-08-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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