利用硬體結構改善電子束微影中鄰近效應及電荷累積效應

Abstract

隨著半導體工業的快速發展及積體電路製程上的微縮，微影技術是推動著莫爾定律繼續前進的關鍵技術，電子束微影及EUV是未來勢在必行的發展技術，當要製作微小及密度高的積體電路時，電子束微影更是最佳的選擇，另一方面，隨著尺寸微縮，微影圖型的均勻性嚴重影響著電晶體的臨界電壓及漏電流，亦是急需解決的課題。 本篇論文主要貢獻分兩部分，我們提出一套分析流程，觀測巨觀微影圖形尺寸及品質與微觀下電子的運行軌跡，第二部份針對電子束微影建立基板環境的設計標準及方法，有效解決電子束中的鄰近效應(Proximity Effect)及電荷累積效應(Charging Effect)，這些效應即是限制電子束解析度的關鍵因素。 微影圖形上依據ITRS標準使用線形圖形的線寬(LW)及邊緣粗糙程度(LER)，除此之外，為了分析電子注入基板後的運行機制，我們利用圈環法(Doughnut)實驗求得電子曝光強度分布。 以此分析流程，在不同特性的基板進行一系列實驗，歸納出理想的微影基板製作的標準；首先，我們發現利用二氧化矽薄膜可有效降低電子束鄰近效應，使曝光顯影圖形趨近於所設計圖形，探究電子注入基板後的物理現象，發現氧化層薄膜有效降低電子的背向散射能量，使得注入區域外的額外曝光降低，集中電子束的能量分布範圍。 接著在基板上設計接地金屬的結構，實驗結果顯示存在接地金屬結構的基板，可以製作出狹窄的線寬，能進一步逼近線寬的極限，在電子曝光強度分布上觀察出造成此現象的原因，我們發現有了接地金屬結構的基板，有效解決電子於基板上的累積，使電子偏移的現象降低，電子正向散射的範圍大幅縮小。 最後我們透過改變光阻厚度、增加氧化層厚度及改變接地鈦金屬位置，將導電度及原子序不同的材料基板進行圈環法的實驗，我們發現了電子散射及電荷累積問題存在的關聯性，這現象將顯著影響電子束微影的品質，也將是我們在未來將會深入探討的課題；論文最後我們提出一基板設計的方法，包括沉積薄氧化層及建置接地金屬結構，在此結構上進行電子束微影，可達到最佳的電子束解析度以及最細的線寬。

In the near future, most integrated circuits will be made by e-beam or EUV technique. Especially, as anufacturers seek to make ever smaller and denser chips, e-beam lithography will be the method of choice. But there are still some problems with small chips. The leakage current is a crucial one. One of the reasons to anticipate gate leakage variability is gate line edge roughness (LER). Higher LER always degrades the transistor leakage current. This phenomenon occurs distinctly in small size transistors. In this thesis, we adopt a quantitative research method to analyze the performance of E-beam beam lithography. By using this analytical procedure, we design an ideal substrate to solve the nonideal effects in E-beam lithography. In this substrate, we can make patterns of smaller sizes and with uniform edges. First, we use two quantitative research methods to obtain detailed information in E-beam lithography. One is the doughnut experiment. We use it to get the parameters in E-beam exposure intensity distribution (EID). Using these parameters, we can calculate the electron exposure intensity and distribution. Further analysis of EID provides us with, information about the election’s scattering and trajectory. The second method is followed by ITRS’s standard. Using the SEM image of a developed pattern and image processing, we measure the line width (LW) and line edge roughness (LER). These are the important parameters that define the quality of lithography technology.

As the end of this thesis, we put forward a series of methods to design the ideal substrate for E-beam Lithography. These methods combine depositing oxide films and manufacturing grounded metal structures. Oxide films on substrates suppress the backscattering electrons. And the grounded structures can minimize the effect that charged electrons have of distorting the trajectory of the incident electron beam. Using these two methods, we find that the resulting patterns on this designed substrate have the best quality. Moreover the patterns have narrower line width and smaller line edge roughness. With this novel method, e-beam lithography system may turn into a powerful tool for manufacturing denser chips with greater quality.