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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 管傑雄 | |
dc.contributor.author | Jong-Lih Li | en |
dc.contributor.author | 黎中立 | zh_TW |
dc.date.accessioned | 2021-06-16T17:51:28Z | - |
dc.date.available | 2012-08-16 | |
dc.date.copyright | 2012-08-16 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-13 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64509 | - |
dc.description.abstract | 在鋁/矽材料系統中,其接觸導電特性(GC)及鋁結晶化皆可用建置在矽基材表面之方形孔洞陣列結構增進之,而此陣列結構是以電子束曝光顯影技術來製造的,同時,該導電特性隨著孔洞尺寸之縮小而增進,其導電值由0.004µs增加至13.39µs。穿透式電子顯微鏡分析結果顯示鋁晶粒皆出現於孔洞內或其附近。鋁結晶化比例參數(AC) 由0.007增進至0.359, 該參數則定義為在一個測試腳位中結晶區域之總面積除以該腳位之面積。所發展出之實驗模型顯示GC正比於AC除以介面氧含量之平方。另以改變孔洞佔有率之列系樣品獲得此陣列結構功能之再次確認,為獲致更好之導電效應,並將具孔洞陣列樣品以最適條件退火,除獲得了約9200倍之改進外,並透過能量分佈光譜所量得的介面成份分佈結果及拉曼散射分析結果所量得介面應力,發現另一影響蕭特基能障之介面參數:共晶溫度,可供後續介面設計之參考。本研究現以眾所週知之鋁/矽材料系統成功地驗證了所開發之技術方法,也希望能將之擴展運用至其他材料系統,尤其是無法作高摻雜之半導體材料或是須作高溫退火之元件應用。本研究所開發之技術方法具更高的可控制性及穩固性,並將運用尺寸之目標設定在孔洞製作之最小極限。在此同時,鋁/矽材料系統先天上之運用限制也可一併予以解決。 | zh_TW |
dc.description.abstract | A well-patterned metal-semiconductor interface with square-hole array on a semiconductor substrate, fabricated by electron-beam lithography, is used to improve metal-semiconductor-contact conductance (MSCC) by tuning Schottky barrier through designing arrayed nano-scale interfaces. The MSCC increases with decreased hole size from 800, 400, to 200nm. Then, the well-known Al/Si system is applied as the vehicle to verify the newly developed methodology. It is also expected that the contact problems in P-type GaN can be improved.
Instead of conventional heavy-doping or annealing process, the developed methodology can be used to improve the MSCC from 0.004 to 13.390 µS in compared to the sample without holes. The cross-section TEM results show that the hole arrays are fully covered by the deposited Al film. The Al nanocrystals, with in-plane grain sizes around 100nm, appear inside and near the holes. The increase of Al crystallization (AC) further shows the functionality of the smaller holes. In hole-pitch dependence experiment, the hole-array areas are also verified as the active areas of the conductance. Therefore, the nano-crystalline Al/Si interfaces are the areas contributing to the larger conductance. In addition, the interfacial oxygen content (PC) decreasing with hole sizes can be explained by the AC increment. Both results agree very well with the size dependence of the MSCC. Hence, an experimental model, expressed as that MSCC is proportional to AC divided by the square of PC, is also established. Compared with other methodologies, the present methodology has the advantages of the higher flexibility of designing, uniformity of manufacturing and compatibility with the semiconductor processing. Moreover, the result verifies that the MSCC can be improved and designed through the developed methodology. For further improving MSCC, the hole-array sample is also annealed and optimized. The best MSCC is about 76.46 µS/cm2, which is around 9200 times better than that of annealed sample without holes. And the annealing temperature of 340℃ is 110℃ lower than that of the conventional processing. To ascribe the effect with a different scenario, currently, a Raman scattering investigation is also conducted. The Al/Si interfacial stress, found in the annealed samples, is also calculated. The result can explain an obviously Si-rich interface, and which can influence Schottky barrier, with a lower PC in the best annealed hole-array sample. Moreover, the functionality of hole array has been successfully identified. The results based on engineering the metal-semiconductor interface promises the possibility to be an alternative other than conventional ones to achieve ohmic contacts, especially for the nanodevices that can not be heavily doped and fabricated through high-temperature processing. Most significantly, a more robust and well-controlled interface can be obtained and expected to overcome the obstacles in the newly introduced materials systems and the devices with their size reduced to the deep nano-scale domain. Meanwhile, the inherently non-planar Al/Si interface can be prevented. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T17:51:28Z (GMT). No. of bitstreams: 1 ntu-101-D91943020-1.pdf: 1767753 bytes, checksum: 4a8f5a0d70c18270640049294fa88e3c (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 目 錄
論文口試委員審定書………………………………………………….i 英文審定書…………………………………………………………….ii 致謝…………………………………………………………………….iii 中文摘要…………………………………………………………….....iv 英文摘要……………………………………………………………….vi 目錄.........................................................................................................ix 圖目錄………………………………………………………………….xi 表目錄………………………………………………………………….xiii 第一章 前言…………………………………………………………...1 1.1目的與動機……………………………………………….1 1.2論文架構………………………………………………….2 第二章 發展背景……………………………………………………...4 2.1電子束技術……………………………………………….4 2.2材料介面工程…………………………………………….8 2.3設計理念………………………………………………….11 第三章 實驗樣品製備………………………………………………...14 3.1 圖型設計…………………………………………………14 3.2 量測結構設計……………………………………………14 3.3 製作流程………………………………………………....15 第四章 量測結果與討論……………………………………………...18 4.1 系列(一)樣品結果及介面檢測………………………….18 4.1.1 電性量測…………………………………….........18 4.1.2 TEM檢測.................................................................20 4.1.2.1 介面微觀結構……………………………20 4.1.2.2 介面之氧及模型建構……………………30 4.2 系列(二)樣品結果及功能驗證………………………….33 4.3 溫度效應…………………………………………………38 4.4 退火效應……………………………………………........41 4.4.1 MSCC量測……………………………………......41 4.4.2 拉曼散射分析………………………………….....44 4.4.3 介面成份分析………………………………….....46 第五章 結論……………………………………………………….......52 參考文獻…………………………………………………………….....53 | |
dc.language.iso | zh-TW | |
dc.title | 以方形孔洞陣列之介面設計增進金屬/半導體接觸
導電特性 | zh_TW |
dc.title | Improving Metal-Semiconductor Contact Conductance
with Patterned Interface of Square-Hole Array | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 王維新,林浩雄,陳啟東,荊鳳德,孫建文 | |
dc.subject.keyword | 接觸導電特性,電子束曝光顯影,穿透式電子顯微鏡,拉曼散射,介面應力,蕭特基能障,共晶溫度, | zh_TW |
dc.subject.keyword | metal-semiconductor-contact conductance,electron-beam lithography,crystallization,nano-crystals,Raman scattering,Schottky barrier,non-planar interface, | en |
dc.relation.page | 57 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-08-13 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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