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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 王暉 | |
| dc.contributor.author | Hsin-Chiang Liao | en |
| dc.contributor.author | 廖信強 | zh_TW |
| dc.date.accessioned | 2021-06-16T17:40:28Z | - |
| dc.date.available | 2016-08-17 | |
| dc.date.copyright | 2012-08-17 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-14 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64318 | - |
| dc.description.abstract | 本論文涵蓋兩個研究方向，第一部分是針對在 V 頻帶之正交調變器 (I/Q modulator) 的設計分別提出被動元件的改良以及一個嶄新的方法來改善正交不匹
配性 (I/Q mismatch) 。而另一部份將探討有關在次毫米波 (sub-millimeter-wave) 功率放大器 (power amplifier) 之設計方法。 首先，第一部分呈現了一個實現於台積電 90 奈米金氧半場效電晶體 (CMOS) 製程之 V 頻帶寬頻正交調變器。為了改善於設計正交耦合器時所產生的正交不匹配性，我們使用了一個具有低振幅且相位不匹配以及對端點阻抗低敏感特性之共平面波導指叉式耦合器 (CPW interdigitated coupler) 。同時，藉由修改傳統馬遜式平衡與不平衡轉換器 (Marchand-type balun) 之接地平面結構，本地振盪源的漏流效應 (LO leakage) 也得到良好的抑制。另一個使用穩茂 0.15 微米假晶式高電子遷移率電晶體 (pHEMT) 製程之正交調變器引入了一個名為功率鎖定迴路 (power-locked loop) 系統之新穎的功率校正方法來達到寬頻的鏡像訊號抑制 (sideband suppression) 。此功率鎖定迴路系統運用了回授機制使正交不匹配性得以自動化調整，同時也克服了傳統耦合器在頻寬上的限制。上述兩個 V 頻帶之正交調變器分別呈現了大於 28 與 35 dBc 鏡像抑制率並擁用大於 17 GHz 的頻寬。此外，降低正交不匹配性對於整體系統向量強度錯誤率 (error vector magnitude, EVM) 的貢獻也經由高達 7 Gb/s 之高速傳輸實驗得到驗證。 此論文的第二部分闡述了一個異於傳統阻抗轉換的電路架構，並成功經由一個實現於台積電 65 奈米金氧半場效電晶體製程之 D 頻帶功率放大器驗證。作者於此提出的阻抗轉換網路可同時具備阻抗匹配以及功率結合的功能，並提供了多路功率結合的方法，目的在於提高整體輸出功率與提升效率。而多路功率結合產生的高阻抗傳換比在提出的阻抗轉換網路中也可解決，其結果可由大於 30 GHz 的小訊號頻寬來驗證。且因免除了額外的功率結合架構，此操作於 150 GHz 頻段之功率放大器於一小晶片面積內實現了大於 12 dBm 的飽和功率與 12% 的功率附加效率 (power-added efficiency, PAE)。 | zh_TW |
| dc.description.abstract | This thesis is composed of two main researches. The first part is the investigations on two V-band I/Q modulators including the improvements on passive components and a creative method to enhance the I/Q balance, and the other part is the design topic about sub-millimeter-wave power amplifier.
The first part starts with a V-band wideband I/Q modulator implemented in TSMC 90-nm CMOS process. In order to improve the I/Q mismatch in the design of quadrature phase, a co-planar waveguide (CPW) interdigitated coupler with low amplitude and phase imbalances and insusceptibility to port impedance is employed. The LO leakage is also effectively mitigated by revising the conventional Marchand-type baluns with incomplete ground plane. Another I/Q modulator fabricated in WIN’s 0.15-um pHEMT technology features wideband sideband suppression ratio with the novel power-level calibration method, power-locked loop system. A feedback mechanism is introduced to improve I/Q mismatch automatically and also overcomes the bandwidth restriction on conventional couplers. The two proposed I/Q modulators demonstrate lower than -28 and -35 dBc sideband suppression ratio, respectively, with wider than 17 GHz bandwidth. Moreover, the capability to minimize the I/Q mismatch contribution to system error vector magnitude (EVM) is verified by 7 Gb/s high speed transmission experiments. The second part presents the proposed impedance transformation network exemplified by a D-band power amplifier in TSMC 65-nm CMOS. In order to increase the output power and enhance the efficiency, the impedance transformation network integrates matching and power combining network simultaneously and also provides the solution of multi-ways power combining. The large impedance transformation ratio resulting from multi-way power combining can also be resolved in the procedure of proposed impedance transformation network. This can be verified by the small signal bandwidth of wider than 30 GHz. Furthermore, without additional power combining structures, higher than 12 dBm saturation power and 12 % power-added efficiency (PAE) are achieved with a compact chip size around 150 GHz. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T17:40:28Z (GMT). No. of bitstreams: 1 ntu-101-R99942028-1.pdf: 28217139 bytes, checksum: 9cc53da1d77fbba05ccbe5339b532cbe (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 iii ABSTRACT v CONTENTS vii LIST OF FIGURES xi LIST OF TABLES xxi Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Literature Survey 3 1.2.1 MMW I/Q Modulator 3 1.2.2 D-band Power Amplifier 6 1.3 Contributions 8 1.4 Thesis Organization 10 Chapter 2 Design of High Sideband Suppression Ratio I/Q Modulators and Demodulators 11 2.1 Digital Modulation 11 2.1.1 Phase Shift Keying (PSK) 11 2.1.2 Frequency Shift Keying (FSK) 12 2.1.3 Quadrature Amplitude Modulation (QAM) 13 2.1.4 Orthogonal Frequency-division Multiplexing (OFDM) 14 2.1.5 Intersymbol Interference (ISI) 17 2.1.6 Error Vector Magnitude (EVM) on Constellation Diagram 18 2.2 Basic of I/Q Modulator and Demodulator 21 2.2.1 I/Q modulator and demodulator used in direct-conversion system 21 2.2.2 Operational principle of I/Q Modulator and Demodulator 22 2.2.3 I/Q Impairment on EVM performance 26 2.2.4 Sideband suppression of I/Q modulator 29 2.3 Design of V-band CMOS Broadband High Sideband Suppression Ratio I/Q Modulator adopting Improved Marchand-type Balun and CPW Quadrature Coupler 32 2.3.1 Introduction 32 2.3.2 Modulator Architecture 32 2.3.3 Circuit Design 33 2.3.3.1 Process Description 33 2.3.3.2 Gilbert-cell Mixer 35 2.3.3.3 Improved Marchand-type Balun 44 2.3.3.4 CPW Quadrature Coupler 46 2.3.3.5 I/Q Modulator Performances 51 2.3.4 Experimental Results 53 2.3.5 Discussions 60 2.3.5.1 Analysis of Balun Mismatch Effect on Modulator Performance 60 2.3.5.2 Comparison between CPW Quadrature Coupler and Conventional Quadrature Coupler 69 2.3.6 Performance Summary 76 2.4 Design of V-Band High Data Rate Modulator and Demodulator with Power-Locked Loop LO Source in 0.15-um GaAs pHEMT Technology 77 2.4.1 Introduction 77 2.4.2 Concept of Power-Locked Loop System 77 2.4.3 System Architecture 79 2.4.4 Sub-circuit Design 81 2.4.4.1 Power Budget Calculation 81 2.4.4.2 Sub-harmonically Pumped (SHP) Mixer 83 2.4.4.3 Amplitude Detector 83 2.4.4.4 Buffer Amplifier 84 2.4.4.5 Phase-shifter 85 2.4.4.6 Attenuator 86 2.4.4.7 Operational Amplifier 87 2.4.4.8 Feedback Stability Study 88 2.4.5 Measured Results 91 2.4.5.1 Modulator characteristics 93 2.4.5.2 Demodulator characteristics 100 2.4.6 Discussions 111 2.4.6.1 Limitations of the work 111 2.4.6.2 Discrepancy in the phase-controlled voltage and feedback voltage 112 2.4.6.3 Improvement of 2LO leakage in the sub-harmonic I/Q modulator 114 2.4.6.4 2LO leakage influence on high-speed transmission quality 117 2.4.7 Performance Summary 120 2.5 Summary of Two V-band I/Q Modulators 124 Chapter 3 High Frequency Power Amplifier Design 125 3.1 Power Combining Techniques for MMW PAs 125 3.1.1 Introduction 125 3.1.2 Direct Combining 125 3.1.3 Wilkinson Combiner/Splitter 126 3.1.4 Quadrature Combiner/Splitter 128 3.1.5 Transformer 129 3.1.6 Distributed Active-Transformer (DAT) 131 3.2 Design of A 1.2V Broadband D-band Power Amplifier with 13.2-dBm Output Power in Standard RF 65-nm CMOS 135 3.2.1 Introduction 135 3.2.2 Concept of the Proposed Impedance Transformation Network 136 3.2.3 Circuit Design and Simulation Results 139 3.2.4 Measurement Results 153 3.2.5 Discussions 158 3.2.5.1 Interpretation the inconsistencies of the return loss 158 3.2.5.2 Discussion of wedge and ball bonding wire 162 3.3 Summary 163 Chapter 4 Conclusions 165 REFERENCE 167 | |
| dc.language.iso | en | |
| dc.title | 適用於高速傳輸系統之毫米波高鏡像抑制調變器設計與D頻帶功率放大器之研製 | zh_TW |
| dc.title | Design of Millimeter-wave High Sideband Suppression Ratio Modulator for High Speed Transmission System and D-band Power Amplifier | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡作敏,章朝盛,張鴻埜,林坤佑 | |
| dc.subject.keyword | 正交調變器,V頻帶,共平面波導耦合器,馬遜式平衡與不平衡轉換器,功率鎖定迴路,鏡像抑制,高速傳輸,功率放大器,D頻帶,阻抗轉換,功率結合, | zh_TW |
| dc.subject.keyword | I/Q modulator,V-band,CPW coupler,Marchand balun,power-locked loop,sideband suppression,high speed transmission,power amplifier,D-band,impedance transformation,power combining, | en |
| dc.relation.page | 180 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-08-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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