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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
dc.contributor.author | Sung-Lin Tsai | en |
dc.contributor.author | 蔡松林 | zh_TW |
dc.date.accessioned | 2021-06-16T17:38:03Z | - |
dc.date.available | 2014-08-17 | |
dc.date.copyright | 2012-08-17 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-14 | |
dc.identifier.citation | [1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000.
[2] E. Hegazi and Asad A. Abidi, 'A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-μm CMOS,' IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 782-792, May 2003. [3] R. B. Staszewski, et al., 'All-digital PLL and GSM/EDGE transmitter in 90nm CMOS,' in Proc. ISSCC Dig. Tech. Papers, Feb. 2005, pp. 316-317. [4] S. C. Gupta, 'Status of digital phase locked loops,' Proceedings of the IEEE, vol. 63, pp. 291-306, Feb. 1975. [5] W. Lindsey and C. Chie, 'A survey of digital phase-locked loops,' Proceedings of the IEEE, vol. 69, pp. 410-431, Apr. 1981. [6] R. B. Staszewski, et al., 'A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones,' IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2203-2211, Nov. 2005. [7] R. B. Staszewski, et al., 'All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13μm CMOS,' in Proc. ISSCC Dig. Tech. Papers, Feb. 2004, pp. 272-273. [8] A. Rylyakov, et al., 'Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications,' in Proc. ISSCC Dig. Tech. Papers, Feb. 2009, pp. 94-95. [9] M. Lee, et al., 'A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution,' IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2808-2816, Oct. 2009. [10] R. B. Staszewski and P.T. Balsara, “All-digital frequency synthesizer in deep-submicron CMOS,” JOHN WILEY & SONS, INC., 2006. [11] P. Dudek, et al., 'A high-resolution time-to-digital converter utilizing a Vernier delay line,' IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000. [12] C. M. Hsu, 'Techniques for High-Performance Digital Frequency Synthesis and Phase Control,' PhD Thesis, Massachusetts Institute of Technology, Sep. 2008. [13] M. H. Perrott, M. D. Trott, and C. G. Sodini, 'A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis,' IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1028-1038, Aug. 2002. [14] T. A. Riley, et al., 'Delta-sigma modulation in fractional-N frequency synthesis,' IEEE J. Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May 1993. [15] M. Gupta and B. S. Song, 'A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration,' IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2842-2851, Dec. 2006. [16] S. E. Meninger and M. H. Perrott, 'A 1-MHz bandwidth 3.6 GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise,' IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 966-980, Apr. 2006. [17] C. M. Hsu, et al., 'A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation,' IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2776-2786, Dec. 2008. [18] S. Pellerano, et al., 'A 4.75-GHz fractional frequency divider-by-1.25 with TDC-based all-digital spur calibration in 45-nm CMOS,' IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3422-3433, Dec. 2009. [19] M. Zanuso, et al., 'A wideband 3.6 GHz digital ΔΣ fractional-N PLL with phase interpolation divider and digital spur cancellation,' IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 627-638, Mar. 2011. [20] X. Yu, et al., 'An FIR-embedded noise filtering method for ΔΣ fractional-N PLL clock generators,' IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2426-2436, Sept. 2009. [21] I. T. Lee, et al., 'A 6-GHz all-digital fractional-N frequency synthesizer using FIR-embedded noise filtering technique,' IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 5, pp. 267-271, May 2012. [22] H. Huh, et al., 'Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer,' IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2228-2236, Nov. 2005. [23] Y. C. Yang and S. S. Lu, 'A CMOS ΔΣ fractional-N frequency synthesizer with quantization noise pushing technique,' in Proc. IEEE Symposium on VLSI Circuits, June 2007, pp. 262-263. [24] W. H. Chiu and T. H. Lin, 'A 3.6GHz 1MHz-bandwidth ΔΣ fractional-N PLL with a quantization-noise shifting architecture in 0.18μm CMOS,' in Proc. IEEE Symposium on VLSI Circuits, June 2011, pp. 114-115. [25] I. Galton, 'One-bit dithering in delta-sigma modulator-based D/A conversion,' IEEE ISCAS, pp. 1310-1313, May 1993. [26] T. H. Lin, et al., 'Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs,' IEEE Trans. Circuits Syst. - I, Reg. Papers, vol. 56, no. 5, pp. 877-885, May 2009. [27] R. Staszewski, et al., 'Elimination of spurious noise due to time-to-digital converter,' IEEE Dallas Circuits and Systems Workshop, pp. 67-70, Oct. 2009. [28] E. Temporiti, et al., 'A 3.5 GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation,' IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2723- 2736, Dec. 2010. [29] H. Y. Jian, et al., 'A fractional-N PLL for multiband (0.8-6 GHz) communications using binary-weighted D/A differentiator and offset-frequency ΔΣ modulator,' IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 768-780, Apr. 2010. [30] W. H. Chiu, Y. H. Huang, and T. H. Lin, 'A 5GHz phase-locked loop using dynamic phase-error compensation technique for fast settling in 0.18-μm CMOS,' in Proc. IEEE Symposium on VLSI circuits, June 2009, pp. 128-129. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64272 | - |
dc.description.abstract | 本篇論文實現了一個量化雜訊抑制的全數位小數型鎖相迴路。針對三角積分調變器所造成的量化雜訊與小數突波進行改善。此技巧透過產生新的調變路徑,量化步階與調變頻率皆可以獨自設計而不受迴路參數影響。量化雜訊能量可以因而減少且集中在高頻。此外藉由增加調變器的輸入並且在數位迴路前補償的方式,小數突波也因此被移動到高頻。因此,量化雜訊與小數突波可被迴路更有效率的抑制。
此量化雜訊抑制技巧實現於一個36億赫茲頻帶的全數位鎖相迴路。使用台積電90奈米製程,整個系統操作在1.2-V共花費9.25 mA電流。在36億赫茲下,所量測到的參考突波為 -70 dBc。相位雜訊於10-MHz頻率誤差下從 -90 dBc/Hz改善成 -121 dBc/Hz。小數突波也被抑制了5 dB。 | zh_TW |
dc.description.abstract | This thesis presents a quantization noise suppression technique for all-digital fractional-N PLL to address the quantization noise and fractional spur issues from the ΔΣ modulator. The proposed technique builds a new modulation path that allows the quantization step and modulation frequency to be designed independently and not limited by the loop parameters. The quantization noise power is thus reduced and shifted to higher frequency offset. In addition, by increasing modulator input value and compensating later in digital domain, the fractional spur is also shifted to higher frequency offset. Therefore, both quantization noise and fractional spur are filtered by the loop more effectively.
The proposed technique is implemented in the design of a 3.6-GHz ADPLL. Fabricated in the TSMC 90-nm CMOS technology, the whole system dissipates 9.48 mA from a 1.2-V supply. At 3.6 GHz, the reference spur at 25 MHz offset is -70 dBc and the phase noise measured at 10-MHz offset is reduced from -90 dBc/Hz to -121 dBc/Hz. The fractional spur is also reduced by 5 dB. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T17:38:03Z (GMT). No. of bitstreams: 1 ntu-101-R98943022-1.pdf: 2801242 bytes, checksum: 03b2cdcc9fab11a26056a8b27109f17b (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | Chapter 1 Introduction .................................................................................................... 1
1.1 Motivation .............................................................................................................. 1 1.2 Thesis Overview ..................................................................................................... 2 Chapter 2 Introduction to All-Digital Phase-Locked Loops .......................................... 3 2.1 Basics of Analog Phase-Locked Loops .................................................................. 3 2.2 Background of All-Digital Phase-Locked Loops ................................................... 5 2.3 Basics of ADPLL Building Blocks and Modeling ................................................. 7 2.3.1 Phase-Frequency Detector and Time-to-Digital Converter ............................. 8 2.3.2 Digital Loop Filter and Digital-Controlled Oscillator ................................... 10 2.3.3 Frequency Divider ......................................................................................... 12 2.4 Summary ............................................................................................................... 13 Chapter 3 Introduction to Fractional-N PLLs ............................................................. 15 3.1 Introduction .......................................................................................................... 15 3.2 Background ........................................................................................................... 15 3.3 Principle of Classical Fractional-N PLLs ............................................................. 16 3.4ΔΣ Fractional-N PLLs ......................................................................................... 18 3.5 Tradeoff between Quantization Noise and Bandwidth......................................... 23 3.6 Prior Works for Reducing Quantization Noise..................................................... 25 3.6.1 Error Cancellation Technique ........................................................................ 25 3.6.2 Fractional Phase Technique ........................................................................... 27 3.6.3 Quantization Noise Filtering ......................................................................... 29 3.6.4 Increasing Modulation Frequency ................................................................. 31 Chapter 4 A 3.6-GHz Band All-Digital ΔΣ Fractional-N PLL with Quantization Noise Suppression Technique ....................................................................................... 35 4.1 Introduction .......................................................................................................... 35 4.2 Quantization Noise Suppression Technique ......................................................... 36 4.2.1 Quantization Noise Shifting Technique ........................................................ 36 4.2.2 Fractional Spur Shifting Technique ............................................................... 42 4.3 Analysis and Modeling of QNS Technique .......................................................... 49 4.3.1 Modeling of QNS Technique ........................................................................ 49 4.3.2 Effectiveness of Quantization Noise Reduction ............................................ 52 4.3.3 Effect of Nonlinearity .................................................................................... 55 4.4 System Design ...................................................................................................... 61 Chapter 5 Implementation of a 3.6-GHz All-Digital Fractional-N PLL ..................... 69 5.1 System Architecture ............................................................................................. 69 5.2 PFD and Time-to-Digital Converter ..................................................................... 70 5.3 2nd-order Digital Loop Filter ................................................................................ 73 5.4 Digital Controlled Oscillator ................................................................................ 78 5.5 Frequency Divider and Multiplier ........................................................................ 85 5.6 QNS Processor ...................................................................................................... 89 5.7 Simulation Results ................................................................................................ 91 Chapter 6 Measurement Results ................................................................................... 93 6.1 Measurement Setup .............................................................................................. 93 6.2 Chip Pin Configuration and Printed Circuit Board Design .................................. 94 6.3 Experimental Results ............................................................................................ 96 6.3.1 Measurement Results with QNS Technique Enabled .................................... 98 6.3.2 Measurement Results with Fractional Spur Shifting Technique Enabled ... 101 6.4 Summary ............................................................................................................. 104 Chapter 7 Conclusions and Future Works ................................................................. 107 7.1 Conclusions ........................................................................................................ 107 7.2 Future Works ...................................................................................................... 108 References .................................................................................................................... 109 | |
dc.language.iso | en | |
dc.title | 具量化雜訊抑制之全數位小數頻率合成器 | zh_TW |
dc.title | A Quantization Noise Suppression Technique for All-Digital Fractional-N PLLs | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),李泰成(Tai-Cheng Lee),黃柏鈞(Po-Chiun Huang) | |
dc.subject.keyword | 全數位小數頻率合成器,量化雜訊,小數突波,時間數位轉換器,鎖相迴路, | zh_TW |
dc.subject.keyword | All-digital Fractional-N Frequency Synthesizer,Quantization Noise,Fractional Spur,Time-to-Digital Converter,Phase-Locked Loop, | en |
dc.relation.page | 112 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-08-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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