請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64219
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 張帆人 | |
dc.contributor.author | Yu-Cheng Chen | en |
dc.contributor.author | 陳佑政 | zh_TW |
dc.date.accessioned | 2021-06-16T17:35:23Z | - |
dc.date.available | 2017-08-20 | |
dc.date.copyright | 2012-08-20 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-14 | |
dc.identifier.citation | [1] V. Kaenel, “A high-speed, low-power clock generator for a microprocessor application,” IEEE J. Solid-State Circuits, vol. 33, pp. 1634–1639, Nov. 1998.
[2] C. Liang, H. Chen, and S. Liu, “Spur-suppression techniques for frequency synthesizers,” IEEE Trans. Circuits Syst. II: Expr. Briefs, vol.54, no. 8, pp. 653–657, Aug. 2007. [3] B. Razavi, “Challenges in the design of frequency synthesizers for wireless applications,” in Proc. 1997 IEEE Custom Integrated Circuits Conf., May 1997, pp. 395–402. [4] J. Savoj and B. Razavi, “Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems,” Design Automation Conference, pp. 121-126, 2001. [5] M. Meghelli, B. Parker, H. Ainspan, and M. Soyuer, “SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems,” IEEE J. Solid-State Circuits, vol. 35, pp. 1992–1995, Dec.2000. [6] F. M. Gardner, Phaselock Techniques. John Wiley, New York, NY, third ed., 2005. [7] A. Lacaita, S. Levantino, and C. Samori, Integrated Frequency Synthesizers forWireless Systems. NewYork: Cambridge Univ. Press, 2007. [8] K. Shu et al., CMOS PLL Synthesizers: Analysis and Design. NewYork: Springer-Verlag, 2005. [9] A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS oscillators with switched tuning,” in Proc. IEEE Custom Integrated Circuits Conf., May 1998, pp. 555–558. [10] C. Kuo, J. Chang, and S. Liu, “A spur-reduction technique for a 5-GHz frequency synthesizer,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 3, pp. 526–533, Mar. 2006. [11] S. Cheng, H. Tong, J. S. Martinez, and A. I. Karsilayan, “Design and analysis of an ultrahigh-speed glitch-free fully differential charge pump with minimum output current variation and accurate matching,” IEEE Tran. Circuits Syst. II, Exp. Briefs, vol. 53, no. 9, pp. 843–847, Sep. 2006. [12] C. F. Liang, S. H. Chen, and S. I. Liu, “A digital calibration technique for charge pumps in phase-locked systems,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 390–398, Feb. 2008. [13] J. Choi, W. Kim, and K. Lim, “A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL,” IEEE Tran. VLSI Systems, vol. 19, no. 12, 2011. [14] S.-R. Han, C.-N. Chuang, and S.-I. Liu, “A time-constant calibrated phase-locked loop with a fast-locked time,” IEEE Trans. Circuits Syst. II, vol. 54, no. 1, pp. 34–37, Jan. 2007. [15] T. Wu, P. K. Hanumolu, K. Mayaram, and U.-K. Moon, “Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 427–435, Feb. 2009. [16] W. Chiu, Y. Huang, and T. Lin, “A dynamic phase error compensation technique for fast-locking phase-locked loops,” IEEE Journal of Solid- State Circuits, vol. 45, pp. 1137–1149, June 2010. [17] J. R. Burnham, G.-Y. Wei, C.-K. K. Yang, and H. Hindi, “A comprehensive phase-transfer model for delay-locked loops,” in Proc. IEEE Custom Integr. Circuits Conf., 2007, pp. 627–630. [18] C. S.Vaucher, Architectures for RF Frequency Synthesizers. Norwell, MA: Kluwer Academic, 2002, ISBN 1-4020-7120-5. [19] M. Mansuri and C.-K. K. Yang, “Jitter optimization based on phase-locked loop design parameters,” IEEE J. Solid-State Circuits, vol. 37, pp.1375–1382 , 2002. [20] Shizhong Mei, Analysis of Charge Pump Phase Locked Loop in the Presence of Loop Delay and Deterministic Noise. IEEE Proc.51st Midwest Symposium on Circuits and Systems (MWSCAS), 2008, pp.193–196. [21] R. E. Best, Phase-locked loop: Design. Simulation, and Applications, McGraw-Hill International,1997. [22] S. Boyd, L. EL Ghaoui, E. Feron, V. Balakrishnan. Linear Matrix Inequalities in System and Control Theory, SIAM, Philadelphia, 1994 [23] M. C. de Oliveira, J. C. Geromel, J. Bernussou, An LMI optimization approach to multiobjective controller design for discrete-time systems. in Proc. IEEE Conf. Decision Control, 1999, pp. 3611–3616. [24] P. Gahinet, A. Nemirovski, A. Laub, and M. Chilali, LMI Control Toolbox, The MathWorks Inc., Natick, MA, 1995. [25] “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL’s,” National Semiconductor Corp., Application note 1001, July 2001. [26] B. Razavi, RF Microelectronics. New Jersey: Prentice Hall, 1998. [27] W. Rhee, “Design of high performance CMOS charge-pumps in phase locked loops,” in Proc. IEEE Int. Symp. Circuits and Systems, Orlando, FL, May. 1999, pp. II.545–II.548. [28] C. T. Charles and D. J. Allstot, “A calibrated phase/frequency detector for reference spur reduction in charge-pump PLLs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp. 822–826, Sep. 2006. [29] D. Banerjee. (1998). PLL performance, simulation, and design (4th ed.) [Online]. Available: www.national.com [30] A. Aktas and M. Ismail, CMOS PLLs and VCOs for 4G Wireless. Norwell, MA: Springer-Verlag, 2004. [31] X. Gao, et al.,”Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1809-1821, Sep 2010. [32] P. K. Hanumolu, M. Brownlee, K. Mayaram, and U. K. Moon, “Analysis of charge-pump phase-locked loops,” IEEE Trans. Circuits Syst. I,Fundam. Theory Appl., vol. 51, no. 9, pp. 1665–1674, Sep. 2004. [33] Z. Wang, “An analysis of charge-pump phase-locked loops,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 10, pp. 2128–2138, Oct. 2005. [34] C. D. Hedayat, A. Hachem, Y. Leduc, and G. Benbassat, “Modeling and characterization of the 3rd order charge-pump PLL: a fully event-driven approach,” Analog Integrated Circuits and Signal Processing, vol. 19, pp. 25–45, Apr. 1999. [35] M. V. Paemel, “Analysis of a charge-pump PLL: A new model,” IEEE Trans. Commun., vol. 42, pp. 2490–2498, July 1994. [36] F. Gardner, “Charge pump phase-lock loops,” IEEE Trans. Commun.,vol. COM-28, pp. 1849–1858, Nov. 1980. [37] J. P. Hein and J. W. Scott, “z-domain model for discrete-time PLL’s,” IEEE Trans. Circuits Syst., vol. 35, no. 11, pp. 1393–1400, Nov. 1988. [38] Y.C. Chen, F.R. Chang and Y.S. Chou, “Loop Filter Design for Third-order Charge-Pump PLL Using Linearized Discrete-Time Model,” 2010 IEEE Multi-conference on Systems and Control, Yokohama, Japan, Sep. 2010, pp. 2225–2230. [39] Y.C. Chen and F.R. Chang, “An LMI-Based Method for Reference Spur Reduction in Charge-Pump Phase-Locked Loops Containing Loop Delay,” Circuits, Systems, and Signal Processing, Apr. 2012 (online first). [40] Y. S. Chou, Y. C. Chen, W. L. Mao and F. R. Chang, “Loop Filter Design for Phase-Locked Loops with Delay: A Multi-Objective Control Approach,” European Control Conference 2007, Kos Greece, Jul. 2007, pp. 984–991 [41] O. Yaniv, Quantitative Feedback Design of Linear and Nonlinear Control Systems. Norwell, MA: Kluwer, 1999. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64219 | - |
dc.description.abstract | 除了相位雜訊之外,鎖相迴路的輸出訊號包含了突波(spurs)。這兩種不同類型的雜訊影響了輸出訊號的頻譜純淨度。在無線接收機中,突波對於訊號雜訊比的影響是一個棘手的問題。降低迴路頻寬來抑制突波是最直接的方式,然而這會影響到輸出訊號的相位雜訊特性。另一個直接的方式為降低電壓控制震盪器的增益,但這會限制電壓控制震盪器的操作範圍。
本論文係以控制理論為基礎,提出濾波器參數的調整方法來達成突波抑制。考慮了迴路延遲,本論文在z-域來處理濾波器的設計問題,提出以線性矩陣不等式為基礎的設計方法來抑制突波,並且不需要降低迴路頻寬。這個方法適用於三階與四階鎖相迴路的設計。與常見的濾波器設計方法比較,我們的方法能提供更大的突波抑制。 迴路頻寬與抖動峰值(稱為動態參數)的選擇影響了鎖相迴路的性能表現。譬如,頻寬內相位雜訊(in-band phase noise)與頻寬外相位雜訊(out-of-band phase noise)的取捨由迴路頻寬決定。另外,抖動峰值決定迴路穩定度等等。由於製程、電壓以及溫度的變異(PVT variation),迴路濾波器的被動元件、電壓控制震盪器的增益以及電荷幫浦電流的實際值會不同於設計值。因此,實際的動態參數也會不同於設計值,這影響了鎖相迴路的性能表現。 基於z-域的鎖相迴路等效模型,本論文提出一個分析方法,探討迴路濾波器極點的選擇對於動態參數變異的影響。根據分析結果,我們提出了一個濾波器設計策略。當需要大的相位邊限以及動態參數變異主要由電阻變異所影響時,與常見的濾波器設計方法比較,此設計策略不但能降低PVT變異對於動態參數的影響,還能獲得更佳的突波性能。 | zh_TW |
dc.description.abstract | In addition to the phase noise, the output signal of a phase-locked loop (PLL) includes the unwanted spur. The spectral purity of the output signal is determined by the two types of noise. In wireless communication receivers, the spur is a troublesome problem, affecting the signal to noise ratio. The easiest approach to improving the spur performance is to reduce the loop bandwidth. However, this solution affects the phase noise characteristic of the output signal. Another straightforward solution is to decrease the gain of the voltage-controlled oscillator (VCO). The drawback is that this solution limits the operation range of the VCO.
This dissertation presents a loop filter design method to achieve the spur reduction without having to decreasing the loop bandwidth, while considering the loop delay effects. Using control system theory, the dissertation solves the loop filter design problem in the z-domain and proposes an LMI-based method for the spur reduction. This method is applicable to both the third- and fourth-order charge-pump phase-locked loops. Compared to the conventional methods, the proposed method offers greater spur reduction without altering the loop bandwidth. The performances of PLLs mainly depend on the dynamic parameters: the loop bandwidth and the jitter peaking. For example, the loop bandwidth plays an important role in trade-off between the in-band phase noise and the out-of-band phase noise. The jitter peaking directly affects the loop stability. Due to process, voltage, and temperature (PVT) variations, the actual values of the passive components, the VCO gain and the charge-pump current will differ from their designed values. Therefore, the actual dynamic parameters are rarely equal to their well-designed values. This affects the performances of the system. Using a z-domain PLL model, this dissertation presents an analysis method to explore the effects of the loop filter pole on the dynamic parameter changes. Based on the results of the analysis, we propose a design strategy. Compared to the conventional method, this strategy would lessen the effects of the PVT variation on the dynamic parameter and improve the spur performance when the dynamic parameter changes are dominated by the resistor and large phase margin is required. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T17:35:23Z (GMT). No. of bitstreams: 1 ntu-101-D95921008-1.pdf: 676493 bytes, checksum: be14f25648d7270fc23122b62e3b05cf (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | Chapter 1………………………………………………………………1
Introduction……………………………………………………1 1.1 Introduction……………………………………………………1 1.2 Contributions……………………………………………………3 1.3 Organization of This Dissertation…………………………………4 Chapter 2 Basics of Charge-Pump Phase-Locked Loops (CPPLLs)… 5 2.1 Operation Principle of CPPLLs ……………………………5 2.2 Building Blocks of CPPLL………………………………………7 2.2.1 Phase Frequency Detector and Charge Pump…………… 7 2.2.2 Loop Filter …………………………………………11 2.2.3 Voltage-Controlled Oscillator and Frequency Divider…12 2.3 Performance Criteria for Spectral Purity………………………16 2.3.1 Phase Noise……………………………………………16 2.3.2 Reference Spur…………………………………………17 2.4 Phase-Domain Models of CPPLLs……………………………19 2.4.1 Average Current Assumption……………………………19 2.4.2 Weighted Impulse Assumption…………………………22 2.4.3 Dynamic parameters……………………………………23 Chapter 3 CPPLL Modeling and Analysis……………………………25 3.1 z-domain steady-state CPPLL Model…………………………26 3.1.1 Third-order CPPLL……………………………………27 3.1.2 Fourth-order CPPLL……………………………………29 3.2 Jitter Transfer Function Analysis………………………………33 3.3 Summary………………………………………………………38 Chapter 4 LMI-Based Method for Reference Spur Reduction…39 4.1 Preliminaries for Loop Filter Design……………………………40 4.1.1 Ripple Swing in Control Voltage………………………40 4.1.2 Spur Gain ……………………………………………42 4.2 Loop Filter Design………………………………………………44 4.2.1 LMI Formulation of Ripple Swing Control……………44 4.2.2 Jitter Peaking Reduction………………………………45 4.2.3 Loop Filter Design Algorithm…………………………49 4.2.4 Comparisons between the Proposed Methods and the Conventional Ones…54 4.3 Design Example…………………………………………………56 4.3.1 Second-order Loop Filter Design……………………56 4.3.2 Third-order Loop Filter Design…………………………61 4.4 Summary………………………………………………………63 Chapter 5 Analysis of Dynamic parameter Changes………………65 5.1 Loop Bandwidth Change Caused by Inaccurate loop filter……67 5.2 Jitter Peaking Change Caused by Inaccurate loop filter……70 5.3 Discussion……………………………………………………73 5.3.1 Effects of Filter Pole ………………………………73 5.3.2 New Design Strategy……………………………………75 5.3.3 Conventional Design Method…………………………75 5.3.4 Effects of the Variation of the Gain K…………………77 5.4 Numerical Example………………………………………………79 5.5 Summary………………………………………………………84 Chapter 6 Conclusion…………………………………………………85 6.1 Conclusion……………………………………………………85 6.2 Future Work……………………………………………………86 Bibliography……………………………………………………………87 Appendix A ……………………………………………………………93 Appendix B………………………………………………………………95 Appendix C………………………………………………………………99 | |
dc.language.iso | en | |
dc.title | 降低突波與動態敏感性之鎖相迴路分析與設計 | zh_TW |
dc.title | Analysis and Design of Phase-Locked Loops for Reducing Spur and Dynamic Sensitivity | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 林君明,卓大靖,廖德誠,容志輝,曹恆偉 | |
dc.subject.keyword | 抖動峰值,迴路延遲,線性矩陣不等式,迴路頻寬,鎖相迴路,參考突波,製程、電壓以及溫度的變異,z-域, | zh_TW |
dc.subject.keyword | Jitter peaking,Loop delay,Linear matrix inequality (LMI),Loop bandwidth,Phase-locked loop (PLL),Reference spur,PVT variation,z-domain, | en |
dc.relation.page | 99 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-08-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-101-1.pdf 目前未授權公開取用 | 660.64 kB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。