請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64026完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳宗霖(Tzong-Lin Wu) | |
| dc.contributor.author | Tai-Yu Cheng | en |
| dc.contributor.author | 鄭泰禹 | zh_TW |
| dc.date.accessioned | 2021-06-16T17:27:01Z | - |
| dc.date.available | 2015-09-01 | |
| dc.date.copyright | 2012-08-28 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-15 | |
| dc.identifier.citation | REFERENCE
[1] S. Borkar, “Design Challenges of Technology Scaling,” IEEE Micro, vol. 19, no. 4, Jul.-Aug. 1999, pp. 23-29. [2] G. Moore, 'Cramming more components onto integrated circuits,' Electron., vol. 38, no. 8, pp. 114-117, 19 Apr. 1965. [3] A. Chris, “Fifty Years of Moore’s Law,” IEEE Trans. Semiconductor Manufacturing, vol. 24, no. 2, pp. 202, May 2011. [4] F. Schwierz, 'Graphene transistors,' Nature Nanotech, 5, pp. 487-496, 2010. [5] R. R. Tummala, ”SOP: what is it and why? a new microsystem-integration technology paradigm-Moore’s law for system integration of miniaturized convergent systems of the next decade,” IEEE T-AdvP, pp. 241-249, May 2004. [6] R. R. Tummala, ”Packaging: Past, Present and Future,” 6th Int. Conf. Electron. Packag. Technol., 2005. [7] E. Beyne, “The rise of the 3rd dimension for system integration,” in Proc. Int. Technol. Conf., 2006, pp. 1–5. [8] A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, “Three-dimensional integrated circuits,” IBM J. Res. Develop., vol. 50, no. 4/5, pp. 491–506, Jul.–Sep. 2006. [9] W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P.D. Franzon, “Demystifying 3D ICs: The Pros and Cons of Going Vertical,” IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498-510, Nov.-Dec. 2005. [10] M. Motoyoshi, “Through-Silicon Via (TSV),” IEEE Proceedings, vol. 97, no. 1, pp. 43-48, Jan. 2009 [11] M. Rimskog, and T. Bauer, “High Density Through Silicon Via (TSV),” Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, pp. 105-108, Apr. 2008. [12] M. Swaminathan, and A. Ege Engin, Power Integrity Modeling and Design for Semiconductors and Systems, Prentice Hall, 2007. [13] C. Huyghebaert, et al., “Enabling 10μm Pitch Hybrid Cu-Cu IC Stacking with Through Silicon Vias,” Proc. of 60th Electron. Compon. Technol. Conf., Las Vegas, NV, May 2010, pp. 1083-1087. [14] G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. Meindl, “Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication,” in Proc. IEEE Electr. Performance Electron. Packag., 2007, pp. 205–208. [15] J. S. Pak; J. H. Kim; J. H. Cho; K. Y. Kim; T. G. Song; S. Y. Ahn; J. H. Lee; H. D. Lee; K. W. Park; J. H. Kim; , 'PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models,' Compon. Packag. Manuf. Technol., IEEE Transactions on , vol.1, no.2, pp.208-219, Feb. 2011 [16] Z. Xu, X. Gu, M. Scheuermann, K. Rose, B. Webb, J. Knickerbocker and J. Q. Lu, “ Modeling of Power Delivery into 3D Chips on Silicon Interposer,” Proc. IEEE Electron. Compon. Technol. Conf., 2012. [17] X. Hu, P. Du, C. K. Cheng, “Exploring 3D power distribution network physics,” IEEE International Conference on ASIC, pp. 562-565, Oct. 2011. [18] V. F. Pavlidis, and G. D. Micheli, “Power Distribution Paths in 3-D ICs” in Proceedings of ACM Great Lakes Symposium on VLSI, pp. 263-268, May 2009. [19] N. H. Khan, S. M. Alam, and S. Hassoun, “System-Level Comparison of Power Delivery Design for 2D and 3D ICs,” Proc. IEEE Electron. Compon. Technol. Conf., 2009. [20] K. Kang, L. Nan, S. C. Rustagi, K. Mouthaann, J. Shi, R. Kumar, W.-Y. Yin, and L.-W. Li, “A wideband scalable and SPICE-compatible model for on-chip interconnects up to 110 GHz,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 4, pp. 942–951, Apr. 2008. [21] S. P. Sim, S. Krishnan, D. M. Petranovic, N. D. Arora, K. Lee, and C. Y. Yang, “A unified RLC model for high-speed on-chip interconnects,” IEEE Trans. Electron Devices, vol.50, no.6, pp.1501–1510, June 2003. [22] D. Jiao, M. Mazumder, S. Chakravarty, C. Dai, M. J. Kobrinsky, M. C. Harmes, and S. List, “A novel technique for full-wave modeling of large-scale three-dimensional high-speed on/off-chip interconnect structures,” in Proc. Int. Conf. Simulation of Semiconductor Processes and Devices, Sep. 3–5, 2003, pp. 39–42. [23] P. J. Restle, A. E. Ruehli, S. G. Walker, and G. Papadopoulos, “Fullwave PEEC time-domain method for the modeling of on-chip interconnects,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 7, pp. 877–886, Jul. 2001. [24] M. J. Kobrinsky et al., “Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using s-parameters,” in IEEE 12th Topical Meeting Electr. Performance Electron. Packag., 2003, pp. 329–332. [25] J. P. Quine, H. F. Webster, H. H. Glascock, II, and R. O. Carlson, “Characterization of via connections in silicon circuit boards,” IEEE Trans. Microw. Theory Tech., vol. 36, no. 1, pp. 21–27, Jan. 1988. [26] J. Pak, C. Ryu, and J. Kim, “Electrical characterization of through silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation”, IEEE International Conference on Electronic Materials and Packaging, 2007. [27] C. Ryu, et al. “High frequency electrical model of through wafer via for 3-D stacked chip packaging,” in Proc. IEEE Electro. Sys. Integration Tech. Conf., Dresden, Germany, Sept., 2006, pp. 215-220. [28] J. Pak, et al. “Slow wave and dielectric quasi-TEM modes of metal-insulator-semiconductor (MIS) structure through silicon via (TSV) in signal propagation and power delivery in 3D chip package,” in Proc. IEEE Electron. Compon. Technol. Conf., 2010, pp. 667-672. [29] R.-B. Sun, C.-Y. Wen, and R.-B. Wu, “RC Passive Equalizer for Through Silicon Via,” IEEE Electri. Perfor. Electron. Pack. Sys.Conf., 2010, pp. 45-48. [30] K. J. Han, M. Swaminathan, and T. Bandyopadhyay, “Electromagnetic modeling of through-silicon via (TSV) interconnections using cylindrical modal basis functions,” IEEE Trans. Adv. Packag., vol. 33, no. 4, pp. 804–817, Nov. 2010. [31] T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminanthan, and R. Tummala, “Electrical modeling of through silicon and package vias,” in Proc. IEEE Inter. Conf. 3D Syst. Integr., Sep. 2009, pp. 1–8. [32] P. Jain, D. Jiao, X. Wang, and C. H. Kim, “Measurement, analysis and improvement of supply noise in 3D ICs,” in Proc. Symp. VLSI Circuits, 2011, pp. 46–47. [33] I. Ndip, B. Curran, K. Löbbicke, S. Guttowski, H. Reichl, K. D. Lang, H. Henke, “High-Frequency Modeling of TSVs for 3-D Chip Integration and Silicon Interposers Considering Skin-Effect, Dielectric Quasi-TEM and Slow-Wave Modes,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 10, pp. 1627-1641, Oct. 2011. [34] C. Xu, H. Li, R. Suaya, and K. Banerjee, “Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs,” IEEE Trans. Electron Devices, vol. 57, no. 12, pp. 3405–3417, Dec. 2010. [35] W. S. Zhao, X. P. Wang, and W. Y. Yin, “Electrothermal effects in high density through silicon via (TSV) arrays,” Progr. Electromagn. Res., vol. 115, pp. 223–242, 2011. [36] C. R. Paul, Analysis of Multiconductor Transmission Lines, 2nd ed, John Wiley & Sons, 2008. [37] S.-Y. Tang, “The Analysis of Through Silicon Via (TSV) in 3D IC and Application Power Integrity Design,” M.S. thesis, University of Taiwan, Taipei, ON, Taiwan, 2011. [38] C.-D. Wang, S.-Y. Tang, Sally Liu, W. –C. Lo,Y.-P. Chiou, and T.-L. Wu, 'A SPICE-Compatible Model of Multiple TSVs for Crosstalk Prediction in 3-D ICs,' IEEE Microw. Wireless Compon. Lett., submitted for publication. [39] W.Ahmad, L. R. Zheng, Q.Chen, and H. Tenhunen, “Peak-to-Peak Ground Noise on a Power Distribution TSV Pair as a Function of Rise Time in 3-D Stack of Dies Interconnected Through TSVs,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 196-207, Feb. 2011. [40] H. Y. Cheng, “Design of Through-Silicon Via Assignments for Minimizing Simultaneous Switching Noise in 3-D IC,” M.S. thesis, University of Taiwan, Taipei, ON, Taiwan, 2011. [41] A. Yu, J. H. Lau, S. W. Ho, A. Kumar, W. Y. Hnin, D.-Q. Yu, M. C. Jong, V. Kripesh, D. Pinjala, and D.-L. Kwong, “Study of 15 μm Pitch Solder Microbumps for 3D IC Integration.” Proc. Electron. Compon. Technol. Conf., 2009 pp. 6 -10. [42] Henry D. et al, “Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon”, Proc Electron. Compon. Technol. Conf. , Reno, NV, May 2007, pp. 830 – 835. [43] Z. Xu, J. Q. Lu, “High-Speed Design and Broadband Modeling of Through-Strata-Vias (TSVs) in 3D Integration,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 154-162, Feb. 2011. [44] J. -H. Lau, “TSV manufacturing yield and hidden costs for 3D IC integration”, Proc. Electron. Compon. Technol. Conf., 2010, pp. 1031 – 1042. [45] L. Shen et al., “A clamped through silicon via (TSV) interconnection for stacked chip bonding using metal cap on pad and metal column forming in via,” Proc. Electron. Compon. Technol. Conf., 2008, pp. 544-549. [46] Y. -J. Chang, T. -Y. Cheng, H. -H. Chuang, C. -D. Wang, P. -S. Chen, T. -Y. Kuo, C. -J. Zhan, S. -H. Wu, W. -C. Lo, Y. -C. Lu, Y. -P. Chiou, and T. -L. Wu, 'Low Slow-Wave Effect and Crosstalk for Low-Cost ABF-Coated TSVs in 3-D IC Interposer,' in Proc. IEEE Electron. Compon. Technol. Conf.,2012, pp.1934-1938, San Diego, USA, May 2012. [47] C. -C. Chi, E. J. Marinissen, S. K. Goel, and C. –W. Wu. “Post-Bond Testing of 2.5D-SICs and 3D-SICs Containing a Passive Silicon Interposer Base.” In Proceedings IEEE International Test Conference (ITC), September 2011. [48] H. Hasegawa, M. Furukawa, and H. Yanai, “Properties of Microstrip Line on Si-SiO2 System,” IEEE Trans. Microw. Theory Tech., vol. 19, no.11, pp. 869-881, Nov. 1971. [49] D. K. Cheng, Field and Wave Electromagnetics, 2nd ed. Addison Wesley, 1989. [50] R. W. Churchill & J. W. Brown, Complex Variable & Applications, McGraw-Hill, 1984, p.329. [51] A. Bansal, B. Paul, and K. Roy, “An analytical fringe capacitance model for interconnects using conformal mapping,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 12, pp. 2765–2774, Dec. 2006. [52] A. V. Mezhiba, and E. G. Friedman, “Impedance Characteristics of Power Distribution Grids in Nanoscale integrated Circuits,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 11, pp. 1148-1155, Nov. 2004. [53] S. T. Hall & H. L. Heck, Advanced Signal Integrity for High-Speed Digital Designs. A John Wesley & Sons, INC., Publication, 2009. [54] F. W. Grover, Inductance Calculations: Working formulas and Tables. Mineola, New York, USA: Dover Publications, 2009. [55] T. Sakurai and K. Tamaru, “Simple formulas for two- and three-dimensional capacitances,” IEEE Trans. Electron Devices, vol. 30, no. 2, pp. 183–185, Feb. 1983. [56] J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M.-S. Suh, K.-Y. Byun, and J. Kim, “High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV),” Compon. Packag. Manuf. Technol., IEEE Transactions on , vol.1, no.2, pp.181-195, Feb. 2011. [57] J. Cho, E. Song, K. Yoon, J. S. Pak, J. Kim, W. Lee, T. Song, K. Kim, J. Lee, H. Lee, K. Park, S. Yang, M. Suh, K. Byun, and J. Kim, “Modeling and analysis of through-silicon via (TSV) noise coupling and suppression using a guard ring,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 220–233, Feb. 2011. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64026 | - |
| dc.description.abstract | 現在半導體產業界中，晶片製程為了降低成本而一直走向縮小化的趨勢。而這個趨勢也已經被摩爾定律規範出來。不過現有的晶片製程的微影蝕刻技術已經逐漸達到物理的極限。而為了要繼續邁向縮小化的目標，必須要發展一些解決的方式。藉由垂直晶片堆疊的三維積體電路提供了有效的解決方式，可以達到高密度，高效能，以及做到不同功能晶片的系統整合。而在三維積體電路中所使用的堆疊技術中，直通矽晶孔柱，因擁有較短的電氣長度，故可以達成較高效能的傳輸，是目前最備受矚目的技術。
不過，三維積體電路的研發有許多需要解決的問題。其中，電源供應網路的電源完整性設計是其中一個重要的議題，而在三維電源供應的雜訊耦合更為複雜。要能對在電源供應網路的雜訊傳遞進行探討以及設計，準確的建構包含直通矽晶孔柱在內的完整三維積體電路的電源供應網路等效電路模型是必要的。直通矽晶孔柱在走向高密度的製程的趨勢是極有可能的。故在本篇會特別探討一對直通矽晶孔柱在極近距離之下的電氣特性。傳統的直通矽晶孔柱模型無法適用於極近距離的情況，本篇則藉由保角轉換的方式，提出一個改良型的模型而成功進行修正。而當直通矽晶孔柱結合晶片內部電源供應網路時，供應網路的金屬繞線會和半導體的矽表面產生耦合，這堆疊部分的效應需要被考慮。我們也會提出一個適用於考慮這些耦合特性的效果的等效模型。 在提出模型建構的流程之後，為了能運用到較大範圍的三維積體電路結構, 我們建立了電路模型的自動化程序。藉由自動化程序的幫助，大範圍結構的等效電路模型可以立刻產生，經有此電路我們可以做一些結構上的分析與應用．最後搭配一些程序上的設定，我們可以對等效電路的效果及實用性做出一個應用上的規格，方便我們做分析。日後，可以幫助進行電源供應網路的相關設計。 | zh_TW |
| dc.description.abstract | In semiconductor industry nowadays, shrinking the transistor size has been the trend of chip process to reduce the cost. However, since the technique of lithography in chip process has almost reached the physical limit, some solutions are needed to keep following Moore’s law.
Three-dimensional integrated circuit (3-D IC) provides an promising one of the solutions which can reach high density, high performance, and system integration of heterogeneous functionality by vertically stacking the chips. Many stacking technologies have been developed, in which through-silicon via is the most promising one due to its shorter electrical length, and as a result, higher performance of transmission. Nevertheless, there are still many problems needed to be solved in 3-D IC design, where power integrity is one of the most important issues. In order to study and suppress the coupling noise in power delivery network, it is necessary to construct an accurate equivalent circuit model for full power delivery system in 3-D IC. Since high-density process of TSV is the trend, electrical behavior of fine-pitch TSVs will be discussed. Compared to the conventional TSV model, which is not suitable when two TSVs are close, an improved model for fine-pitch TSVs by using conformal mapping is proposed in this thesis. Besides, noticeable coupling between metal in power/ground grids and the TSVs inside the silicon substrate will occur as TSVs are connected to the power/ground grids. This effect is also considered based on the TSV coupling node insertion method (TSV-CNIM) in the equivalent circuit model. Finally, automatic program for generating SPICE netlists of the 3-D IC has been developed in attempt to analyze large-scale 3-D IC structures. Using this automatic program, equivalent circuit model of the PDN in 3-D IC can be generated instantaneously, and the electrical behavior of the PDN can be characterized and designed can be made more efficiently. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T17:27:01Z (GMT). No. of bitstreams: 1 ntu-101-R99942017-1.pdf: 11988323 bytes, checksum: df386859dbbe08709c1cae2457fb80d2 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | CONTENTS
口試委員會審定書 # 誌謝 i 中文摘要 iii ABSTRACT iv ACRONYMS vi CONTENTS vii LIST OF FIGURES x LIST OF TABLES xiv Chapter 1 Introduction 1 1.1 Research Motives 1 1.2 Paper Surveys 3 1.3 Contribution 6 1.4 Thesis Outline 7 Chapter 2 Introduction to 3-D IC and Through-Silicon Via (TSV) 9 2.1 Stacking Technologies 9 2.1.1 Wire Bonding 9 2.1.2 Microbump 10 2.2 Typical Configurations of TSV 11 2.3 Fabrication Process of TSV 12 2.4 Typical 3-D IC Structure 14 Chapter 3 Electrical Model for Through-Silicon Via Structure 17 3.1 Conventional Model for TSV pair 17 3.1.1 The Constraints of the Conventional Method 19 3.1.2 Slow-wave Mode and Dielectric Quasi-TEM Mode for TSV 25 3.2 Proposed Macro-π Model for Two-TSV System 33 3.3 Equivalent Circuit Model for Multi-TSV System 41 3.4 Summary 42 Chapter 4 Electrical Model for Power Distribution Network Structure in Three-Dimensional Integrated Circuit 44 4.1 Typical On-chip PDN Configurations 44 4.2 Equivalent Circuit Model for Power/Ground-Grids System 46 4.2.1 Resistance and Inductance part 46 4.2.2 Capacitance Part 51 4.3 TSV Coupling Node Insertion Method (TSV-CNIM) 59 4.4 Summary 67 Chapter 5 Automated Modeling and Electrical Analysis on Large-Scale and Stacked Power Distribution Networks in Three-Dimension Integrated Circuit 68 5.1 Scenario 68 5.2 Automation Methodology 69 5.2.1 Mesh-Type PDN 70 5.2.2 Via-Type PDN 76 5.2.3 Integration for Mesh-Type PDN and Via-Type PDN 78 5.3 Automation Validation 83 5.3.1 Large-Scale Power/Ground Grids 83 5.3.2 TSV Array 86 5.3.3 Large-scale Power/Ground Grids Stacking with TSV Array 87 5.4 Frequency-domain Analysis 95 5.4.1 Scenario for a Packaged System 95 5.4.2 Macroscopic Model for 3-D IC PDN for Power Integrity Analysis 98 5.4.3 Modeling Benchmark 104 5.5 Summary 111 Chapter 6 Conclusion 113 ACKNOWLEDGMENT 115 REFERENCE 116 PUBLICATION LIST 123 | |
| dc.language.iso | en | |
| dc.subject | 自動化程序 | zh_TW |
| dc.subject | 保角轉換 | zh_TW |
| dc.subject | 電源供應網路 | zh_TW |
| dc.subject | 直通矽晶孔柱 | zh_TW |
| dc.subject | 三維積體電路 | zh_TW |
| dc.subject | 等效電路模型 | zh_TW |
| dc.subject | 電源完整性 | zh_TW |
| dc.subject | automatic programing | en |
| dc.subject | through-silicon via | en |
| dc.subject | power delivery network | en |
| dc.subject | power integrity | en |
| dc.subject | conformal mapping | en |
| dc.subject | equivalent circuit model | en |
| dc.subject | Three-dimensional integrated circuit | en |
| dc.title | 三維積體電路之電源供應網路的模型建置流程與其自動化 | zh_TW |
| dc.title | Power Delivery Network Modeling Methodologies and Automation for Three-Dimensional Integrated Circuit (3-D IC) | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳瑞北(Ruey-Beei Wu),邱奕鵬(Yih-Peng Chiou),盧奕璋(Yi-Chang Lu),盧信嘉(Hsin-Chia Lu) | |
| dc.subject.keyword | 三維積體電路,直通矽晶孔柱,電源供應網路,電源完整性,保角轉換,等效電路模型,自動化程序, | zh_TW |
| dc.subject.keyword | Three-dimensional integrated circuit,through-silicon via,power delivery network,power integrity,conformal mapping,equivalent circuit model,automatic programing, | en |
| dc.relation.page | 123 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-08-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-101-1.pdf 未授權公開取用 | 11.71 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。