互補式金氧半場效電晶體毫米波頻段功率放大器研製與效率改善之研究

Abstract

在本論文中，我們將以高階的金氧半場效電晶體 (CMOS) 進行毫米波功率放大 器的設計與製作。設計重點分別為降低靜態功率消耗改善低功率操作時的效率， 以及輸出功率的提升。 第一部分是以 90 奈米金氧半場效電晶體低功耗製程設計 V 頻段的功率放大 器，並提出一個由峰值檢測器改良而成的自適性偏壓調整電路，這個功率放大器 總共有兩個版本。在沒有使用自適性偏壓 (adaptive bias) 的電路中，小信號增益為16 dB，輸出飽和功率為 13.8 dBm，最大附加功率效率 (PAE)13.5%。在 1dB 增益壓縮時的輸出功率 (OP 1dB ) 為 10.3 dBm，附加功率效率為 7.3%。而在另外一個版本的電路中，小信號增益為 12.7 dB，輸出飽和功率為 12.3 dBm。1dB 增益壓縮時的輸出功率為 10.7 dBm，附加功率效率則提升至 8.3%。透過自動調整偏壓的方式，當功率放大器為靜態操作時，可以節省 57.6% 的直流功耗。 第二部分是使用 65 奈米金氧半場效電晶體製程設計一個Ｗ頻段具有高輸出功 率的功率放大器。我們提出了一種新型的功率結合方式來實現多顆電晶體的功率 結合匹配網路。透過功率結合，這個功率放大器可以達到飽和輸出功率 18.3 dBm 以及在 1dB 增益壓縮時的輸出功率為 17.5 dBm，並有 12.7 dB 的線性增益。此外，為了達到高輸出功率，必須給予電路足夠的直流功耗。在高直流功耗的操作狀態下，電路本身的寄生效應已經變得不可忽略，這些現象也將會一併在論文中探討。 透過本論文得到的成果可以得知，使用金氧半場效電晶體製程設計的毫米波功 率放大器具有相當的競爭力。藉由輸出功率的提升，將能大幅改善金氧半場效電 晶體毫米波系統的效能與傳輸距離，並有助於在高速傳輸與高解析度影像偵測等 系統應用的研發與整合。

In this thesis, we will present two power amplifiers using CMOS processes. These designs based on two different criteria, which are quiescent dc power reduction and high output power delivery. The V-band power amplifier using 90-nm CMOS LP process is designed with the adaptive bias circuit based on envelope detector architecture to control the dc power. Two versions power amplifiers are demonstrated, which are with and without adaptive bias circuit. The measured small signal gain of the PA without adaptive bias is 16 dB. Measured saturation power is 13.8 dBm with peak PAE 13.5% and the OP 1dB is 10.3 dB with PAE 7.3%. In another version, the measured small signal gain of the PA with adaptive bias is 12.7 dB, which saturation power is 12.3 dBm. The OP 1dB is 10.7 dBm with PAE 8.3%. With adaptive bias technique, about 57.6% quiescent dc power consumption can be reduced from 168.6 mW to 72 mW, and the efficiency is also improved in low power operation. The W-wand power amplifier for high output power is presented in 65-nm CMOS process. A design method to realize a large number of transistors combined matching network is proposed to achieve high output power, and several parasitic effects in high dc power operation are also introduced. The power amplifier achieves measured saturation power of 18.3 dBm with peak PAE 9.4%, which OP 1dB is 17.5 dBm and the linear gain is 12.7 dB. To the author’s knowledge, this output power is the highest for CMOS power amplifiers at 94 GHz to date. These results present that CMOS PAs are still competitive at high frequencies, which are beneficial to integrate systems in CMOS for millimter-wave applications such as active imaging systems and high data-rate wireless communications.