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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63836完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Shou-Chen Hsu | en |
| dc.contributor.author | 許守鎮 | zh_TW |
| dc.date.accessioned | 2021-06-16T17:20:26Z | - |
| dc.date.available | 2013-08-19 | |
| dc.date.copyright | 2012-08-19 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-16 | |
| dc.identifier.citation | [1] G. I. Bourdopoulos, A. Pnevmtikakis, V. Anastassopoulos, and T. L. Deliyannis, Delta-Sigma Modulators: Modeling, Design and Applications, Imperial College Press, 2003.
[2] P. Silva, L. Breems, K. Makinwa, R. Roovers, and J. Huijsing , “An IF-to-Baseband ΣΔ Modulator for AM/FM/ IBOC Radio Receivers With a 118 dB Dynamic Range”, IEEE J. Solid-State Circuits, vol. 42, 1076-1089, May 2007. [3] S. R. Norsworthy, R. Schreier and G. C. Temes, “Delta-Sigma Data Converters: Theory, Design and Simulation”, IEEE Press, Piscataway, NJ, 1997. [4] M. Park and M. H. Perrott, ” A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-time ΔΣ ADC with VCO-Based Integrator and Quantizer Implemented in 0.13 μm CMOS,” IEEE J. Solid-State Circuit, vol. 44, pp. 3344-3358, no. 12, Dec. 2009. [5] J. Hamilton, S. Yan, and T. R. Viswanathan, “A Discrete-Time Input ΔΣ ADC Architecture Using a Dual-VCO-Based Integrator,” IEEE J. Solid-State Circuits, vol. 57, no. 11, pp. 848–852, Nov. 2010. [6] M. Z. Straayer, and M. H. Perrott, “A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΔΣ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, Apr. 2008. [7] J. Kim, T.-K. Jang,Y.-G. Yoon, and S.-H. Cho, “Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter,” IEEE Transactions on Circuits and Systems—I: regular papers, vol. 57, no. 1, Jan. 2010. [8] J. Kim, W. Yu, H.-K. Yu, and S.-H. Cho, “A Digital-Intensive Receiver Front-End Using VCO-Based ADC with an Embedded 2nd-Order Anti-Aliasing Sinc Filter in 90nm CMOS,” IEEE International Solid-State Circuits Conference, pp. 176-178, Feb. 2011. [9] S. Rao, B. Young, A. Elshazly, W. Yin, N. Sasidhar, and P. K. Hanumolu, “A 71dB SFDR Open Loop VCO-Based ADC Using 2-Level PWM Modulation,” Symposium on VLSI Circuits, pp. 270-271, June 2011. [10] G. Taylor and I. Galton, “A Mostly Digital Variable-rate Continuous-time ADC ΔΣ Modulator,” IEEE International Solid-State Circuits Conference, pp. 298-299, Feb. 2010. [11] G. Taylor and I. Galton, “A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC,” IEEE J. Solid-State Circuits, vol. 45, pp. 2634-2646, Dec. 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63836 | - |
| dc.description.abstract | 本論文提出如何校正以壓控振盪器為基礎之三角積分器所面臨的非線性影響，特別是校正諧波所導致整體效能的降低。在本論文中，以壓控震盪器為基礎之三角積分器皆為開路操作，雖然開路操作可以避免掉穩定度還有迴授補償延遲的問題，但在整個系統所產生的非理想效應皆會直接的反應在輸出而導致整體效能降低，在所有的非理想效應之中，以壓控震盪器所產生的諧波失真最為嚴重，所以本論文的重心也將就諧波失真的問題進行探討，並提出解決方法。
本論文使用兩種不同的方法來矯正非線性效應的影響-其一前景矯正，使用一測試信號來偵測輸入到輸出的變化，從而導出非線性的係數並加以還原。其二為背景矯正，使用一參考三角積分器來達到矯正非線性的目的。 兩者皆為使用台積電90 nm互補式金氧半製程所實現，使用500 MHz的取樣頻率在10 MHz的頻寬，1.2伏特的供應電源時，分別消耗20毫瓦跟12毫瓦的功率 | zh_TW |
| dc.description.abstract | This thesis presents two calibration techniques to address the linearity issue in VCO-based delta-sigma modulator. Unlike conventional delta-sigma modulator, the VCO-based delta-sigma modulator operates in a open-loop manner which avoids the stability and excess loop delay (ELD) issues. However, the non-linear effect is not suppressed by the loop as it affects output directly. Among all the non-linear effects, the harmonic distortion from VCO is the worst and needs to be addressed.
The first technique utilizes the foreground calibration to recover the distorted output signal. The nonlinearity is detected by sending a fixed input pattern. In the second technique, the background calibration is presented. The nonlinearity of VCO is corrected based on the additional reference ADC. These two techniques are implemented in a TSMC 90-nm CMOS process. The system bandwidth is designed 10 MHz with 500 MHz sampling frequency. The implemented modulator dissipate 20 mW and 12 mW respectively from a 1.2-V supply. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T17:20:26Z (GMT). No. of bitstreams: 1 ntu-101-R98943162-1.pdf: 3570438 bytes, checksum: bdbc7a3d907384993ccd1c49c70c1e2e (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Research Motivation 1 1.2 Thesis Organization 2 Chapter 2 Continuous-Time Delta-Sigma Modulator 3 2.1 Introduction 3 2.2 Quantization Noise 4 2.3 Oversampling 6 2.4 Noise Shaping 8 2.5 Multi-Bit vs. Single-Bit Delta-Sigma Modulator 11 2.6 Non-Ideal Effects in Continuous-Time Delta-Sigma Modulator 11 Chapter 3 VCO-Based Delta-Sigma Modulator 15 3.1 Introduction 15 3.2 Operation of VCO-based DSM 15 3.3 Mathematical Framework 17 3.4 Open Loop Operation 18 3.5 SNR of VCO-based Delta-Sigma Modulator 20 3.6 Nonlinear VCO Transform Function 22 3.7 Non-Ideal Effect of VCO-Based Delta-Sigma ADC 23 3.8 Prior Art 26 3.8.1 Without Calibration 27 3.8.2 With Calibration 30 Chapter 4 Design and Implementation of Linearity Calibration of Ring Oscillator for VCO-Based Delta-Sigma Modulator 33 4.1 Introduction 33 4.2 Foreground Calibration 33 4.2.1 Time Domain Behavior 33 4.2.2 Non-Linearity of VCO 35 4.2.3 Main Idea of Calibration 37 4.2.4 Reverse Function Mapping 38 4.3 System Implementation of Foreground Calibration 42 4.4 Circuit Implementation of Foreground Calibration 46 4.4.1 Voltage-Control- Oscillator (VCO) 46 4.4.2 Ramp Generator 50 4.4.3 Counter and 1-z-1 52 4.4.4 Digital Correction Controller 58 4.4.5 Simulation Result 63 4.5 Background Calibration 65 4.5.1 Time Domain Reference 66 4.5.2 Least Mean Square Algorithm 67 4.6 Circuit Implementation of Background Calibration 71 4.6.1 Voltage-Control- Oscillator (VCO) 71 4.6.2 Reference Delta-Sigma ADC 75 4.6.3 Counter and 1-z-1 80 4.6.4 Least Mean Square Filter 80 4.6.5 Simulation Result 88 Chapter 5 Experimental Results 91 5.1 Test Setup 91 5.2 First Chip (foreground) 92 5.3 Second Chip (background) 95 Chapter 6 Conclusions and Future Work 101 6.1 Conclusions 101 6.2 Future Work 101 References 103 | |
| dc.language.iso | zh-TW | |
| dc.subject | 壓控振盪器 | zh_TW |
| dc.subject | 三角積分器 | zh_TW |
| dc.subject | VCO | en |
| dc.subject | Delta-Sigma Modulator | en |
| dc.title | 以壓控振盪器為基礎且具線性校正技術之三角積分調變器 | zh_TW |
| dc.title | Linearization Techniques for VCO-Based Delta-Sigma Modulator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),林永裕(Tung-Yu Lin),蔡宗亨(Tsung-Heng Tsai) | |
| dc.subject.keyword | 壓控振盪器,三角積分器, | zh_TW |
| dc.subject.keyword | VCO,Delta-Sigma Modulator, | en |
| dc.relation.page | 104 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-08-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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