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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 資訊網路與多媒體研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63701
完整後設資料紀錄
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dc.contributor.advisor洪士灝
dc.contributor.authorChia-Heng Tuen
dc.contributor.author涂嘉恒zh_TW
dc.date.accessioned2021-06-16T17:16:44Z-
dc.date.available2017-08-20
dc.date.copyright2012-08-20
dc.date.issued2012
dc.date.submitted2012-08-18
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[59] Peter Stralen and Andy Pimentel. A high-level microprocessor power modeling technique based on event signatures. Journal of Signal Processing Systems, 60(2):239–250, 2010.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63701-
dc.description.abstract模擬是一種常見用來協助系統設計與最佳化的方法。對於系統層級的最佳化而言,能耗與計算資源的多寡是兩個最重要的限制。為了精確的對系統效能與能耗進行預測,我們必須針對每個硬體元件可能運行的狀態,分別建造能耗與時間模型。此外,在一個真實的模擬環境中,追蹤軟體的執行與硬體使用狀況並適時的模擬輸入輸出系統,則是能夠準確進行預測的關鍵。然而,傳統模擬的方式在實際執行上會有相當的困難。首先,要對一個複雜的系統,建構一個週期精確的模擬環境並不是一件簡單的事情。特別是要開發一個異質多核心的模擬系統的時候。再者,對於I/O頻繁的應用程式,速度較慢的模擬環境會大幅的改變程式行為與效能數據。最後,傳`統的軟體效能剖析工具並沒有辦法在模擬器上面運作。在此情況下,要對複雜的軟體,如:Java應用程式,進行效能分析時會有相當的困難。
本篇論文提出了一個虛擬效能分析的架構(Virtual Performance Analyzer Framework)來解決上述的問題。此架構利用一般仿真器並在其中加入效能與能耗模型,來降低建構一個模擬環境所需的時間。我們提供多種效能與能耗模型,來幫助使用者了解仿真器模擬的速度對軟體行為是否會產生影響。此外,我們提出了一個利用仿真器來建構剖析工具的方法。此方法藉由在仿真器中加入效能與能耗監控的裝置與軟體行為分析器,。另一方面,我們擴展VPA的架構,並利用現有的仿真器來快速建構異質多核心系統的模擬環境。我們加入時間同步的機制與競爭模型(contention model)以正確的估計系統效能。我們已經將此架構實作,並且使用真實的應用程式作為個案研究來展示此架構的實用性。
zh_TW
dc.description.abstractSimulation is a common approach for assisting system design and optimization. For system-wide optimization, energy and computational resources are often the two most critical limitations. Modeling energy-states of each hardware component and time spent in each state is needed for accurate energy and performance prediction. Tracking software execution and hardware utilization in a realistic operating environment with properly modeled input/output is key to accurate prediction. However, the conventional approaches can have difficulties in practice. First, for a complex system, building a cycle-accurate simulation environment is no easy task. This is especially true for a multicore system consisting of different types of processing cores. Secondly, for I/O-intensive applications, a slow simulation would significantly alter the application behavior and change its performance profile. Thirdly, conventional software profiling tools generally do not work on simulators, which makes it difficult for performance analysis of complicated software, e.g., Java applications.
This dissertation presents a virtual performance analysis framework (VPA) to tackle the above problems. The proposed framework eases the effort of building a simulation environment by leveraging the infrastructure of functional emulators and adding performance and power models. Multiple sets of the performance and power models can be selectively used to verify if the speed of the simulated system impacts the software behavior. Furthermore, we develop the methodology to build profiling tools with the functional emulator by adding performance/power monitoring facilities and the software activity analyzer. In addition, we extend the VPA framework to facilitate the construction of an emulation environment for a heterogeneous multicore system via integrating the existing processor emulators. The timing synchronization mechanism and the contention model are also included to give an accurate estimate of system performance. We have prototyped the framework and our case studies of real life applications show that the information provided by our tools are useful for software optimization and system design for complex systems, such as Android smartphones.
en
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Previous issue date: 2012
en
dc.description.tableofcontentsContents
Acknowledgment i
Abstract in Chinese iii
Abstract iv
Contents vi
List of Figures ix
List of Tables xi
1 Introduction 1
1.1 Simulation and Emulation Tools in Literature . . . . . . . . . . . . . . . 3
1.1.1 Cycle-accurate Simulators . . . . . . . . . . . . . . . . . . . . . 4
1.1.2 Full System Emulators and Variants for Performance Estimation . 5
1.1.3 Software-based Power Estimation Tools . . . . . . . . . . . . . . 11
1.1.4 Emulator-based Software Analysis Tools . . . . . . . . . . . . . 13
1.1.5 Parallel Multicore Emulators . . . . . . . . . . . . . . . . . . . . 14
1.2 Overall Architecture of Proposed Framework . . . . . . . . . . . . . . . 16
1.3 Organization of this Dissertation . . . . . . . . . . . . . . . . . . . . . . 21
2 Modeling for Uniprocessor Systems 22
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1.1 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 The Virtual Performance Analysis Framework . . . . . . . . . . . . . . . 25
2.2.1 Virtual Performance Monitoring Unit . . . . . . . . . . . . . . . 27
2.2.2 Virtual Timing Device . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.3 Virtual Power Device . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.4 Sample-Based Profiling . . . . . . . . . . . . . . . . . . . . . . 32
2.2.5 Smart Event Tracing . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 Performance Evaluation for Timing Models . . . . . . . . . . . . . . . . 35
2.3.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3.2 Accuracy vs. Emulation Speed . . . . . . . . . . . . . . . . . . . 37
2.3.3 Comparison between the VPA and Traditional Emulation/Simulation Tools 39
2.4 Performance Evaluation for Peripheral Power Model . . . . . . . . . . . 42
2.4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.4.2 Power Estimation for Youtube Application . . . . . . . . . . . . 45
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3 Modeling for Heterogeneous Multicore Processor Systems 49
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2 Emulation of Heterogeneous Multiprocessor Systems . . . . . . . . . . . 51
3.2.1 Emulating the Hardware Aspects of a System . . . . . . . . . . . 52
3.2.2 Supporting Software Development and Performance Analysis . . 57
3.3 The MCEmu Framework . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.1 Data Processor Controller . . . . . . . . . . . . . . . . . . . . . 62
3.3.2 Timing Synchronization of Processor Cores via VPMU . . . . . . 65
3.3.3 Support for Performance Analysis . . . . . . . . . . . . . . . . . 66
3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.4.1 Emulation of the PAC DUO . . . . . . . . . . . . . . . . . . . . 67
3.4.2 Emulation Speed and Accuracy Delivered by the MCEmu . . . . 70
3.4.3 Comparison between the MCEmu and Conventional ESL Tools . 72
3.4.4 Modeling the Memory Contention . . . . . . . . . . . . . . . . . 73
3.4.5 Multithreaded Simulation and System Design . . . . . . . . . . . 74
3.4.6 The Portability of the MCEmu . . . . . . . . . . . . . . . . . . . 77
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4 Performance and Power Analysis for Emulated Systems 79
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.2 Profiling Android Applications . . . . . . . . . . . . . . . . . . . . . . . 80
4.2.1 YouTube Video Playback . . . . . . . . . . . . . . . . . . . . . . 81
4.2.2 Face Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.2.3 Angry Bird Rio . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.2.4 Performance Prediction for Remote Execution . . . . . . . . . . 85
4.3 Performance Analysis and Debugging for Multicore Applications . . . . . 88
4.3.1 Performance Tuning for CRC32 . . . . . . . . . . . . . . . . . . 89
4.3.2 Performance Debugging for SMG2000 . . . . . . . . . . . . . . 91
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5 Conclusion and Future Works 96
Bibliography 99
dc.language.isoen
dc.subject異質多核心系統zh_TW
dc.subject全系統仿真模擬zh_TW
dc.subject多核心系統仿真模擬zh_TW
dc.subject週期近似仿真器zh_TW
dc.subject能耗模型zh_TW
dc.subject效能模型zh_TW
dc.subject效能分析工具zh_TW
dc.subjectFull system emulationen
dc.subjectheterogeneous multicore systemen
dc.subjectmulticore system emulationen
dc.subjectpower modelingen
dc.subjectperformance modelingen
dc.subjectperformance analysis toolen
dc.subjectcycle-approximate emulatoren
dc.title利用模擬系統進行效能與能耗剖析zh_TW
dc.titlePerformance and Power Profiling with Emulated Systemsen
dc.typeThesis
dc.date.schoolyear100-2
dc.description.degree博士
dc.contributor.oralexamcommittee劉邦鋒,廖世偉,郭大維,徐慰中,施吉昇
dc.subject.keyword全系統仿真模擬,週期近似仿真器,效能分析工具,效能模型,能耗模型,多核心系統仿真模擬,異質多核心系統,zh_TW
dc.subject.keywordFull system emulation,cycle-approximate emulator,performance analysis tool,performance modeling,power modeling,multicore system emulation,heterogeneous multicore system,en
dc.relation.page106
dc.rights.note有償授權
dc.date.accepted2012-08-18
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept資訊網路與多媒體研究所zh_TW
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