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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63657完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 蔡坤諭(Kuen-Yu Tsai) | |
| dc.contributor.author | Shi-Chuan Huang | en |
| dc.contributor.author | 黃實權 | zh_TW |
| dc.date.accessioned | 2021-06-16T17:15:48Z | - |
| dc.date.available | 2022-08-17 | |
| dc.date.copyright | 2012-08-27 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-19 | |
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Emami-Naeini, Feedback Control of Dynamic Systems, Prentice Hall, 2010. [11] The MathWorks - MATLAB and Simulink for Technical Computing, http://www.mathworks.com. [12] Chang, T. H. P., “Proximity effect in electron-beam lithography”, J. Vac. Sci. Technol., vol. 12, pp. 1271-1275, Aug. 1975. [13] M.-S. Su, K.-Y. Tsai, Y.-C. Lu, Y.-H. Kuo, T.-H. Pei, and J.-Y. Yen, “Architecture for next generation massively parallel maskless lithography system (MPML2)”, SPIE Proc., vol. 7637, no. 76371Q, July 2010. [14] S.-Y. Chen, S.-C. Chen, H.-H. Chen, K.-Y. Tsai, and H.-H. Pan, “Manufacturability Analysis of a Micro-Electro-Mechanical Systems–Based Electron-Optical System Design for Direct-Write Lithography”, Jpn. J. Appl. Phys., vol. 49, no. 06GE05, June 2010. [15] S. Y. Chen, K. Y. Tsai, Philip C. W. Ng, H. T. Ng, C. H. Liu, Y. T. Shen, C. H. Kuan, Y. Y. Chen, Y. H. Kuo, C. J. Wu, and J. Y. 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B, vol. 16, pp. 916-919, Apr. 1998. [20] C. A. Spindt, C. E. Hoiland, A. Rosengreen, and L Brodie, “Field-emitter-array development for high-frequency operation”, J. Vac. Sci. Technol. B, vol. 11, pp. 468-473, Apr. 1993. [21] R. D. Jones, R. K. Feeney, J. K. Cochran, and D. N. Hill, “A cricuit mode1 for a family of low-voltage field-emission-array cathodes”, Technical Digest of the 8th IVMC, pp. 72-76, Aug. 1995. [22] R. H. Fowler and L. Nordheim, “Electron emission in intense electric fields”, Proc. Roy. Soc. Lond. A, vol. 119, pp. 173-181, May 1928. [23] The circuit simulation - Simulation Program with Integrated Circuit Emphasis, http://www.synopsys.com/home.aspx. [24] A. S. Sedra and K. C. Smith, Microelectronic Circuits, Oxford Univ. Press, pp. 749-766, 2004. [25] L. Yao, M. Steyaert, W. Sansen, “Fast-settling CMOS two-stage operational transconductance amplifiers and their systematic design”, Proc. ISCAS, vol. 2, pp. 839-842, May 2002. [26] A. S. Sedra and K. C. Smith, Microelectronic Circuits, Oxford Univ. Press, pp. 834-843 (2004). [27] M. Figueiredo, R. Santos-Tavares, E. Santin, J. Ferreira, G. Evans, and J. Goes, “A two-stage fully differential inverter-based self-biased CMOS amplifier with high efficiency”, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 58, pp. 1591 -1603, July 2011. [28] P. R. GRAY, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, pp. 624-625 (2001). [29] A. S. Sedra and K. C. Smith, Microelectronic Circuits, Oxford Univ. Press, pp. 852-855 (2004). [30] National Applied Research Laboratories, Chip Implementation Center, http://www.cic.org.tw/cic_v13/english/cisd/cisd2.jsp. [31] C. Klein, J. Klikovits, L. Szikszai, E. Platzgummer, and H. Loeschner, “Projection Mask-Less Lithography (PML2)”, Microelectron. Eng., vol. 87, pp. 1154-1158, Aug. 2010. [32] Taiwan Semiconductor Manufacturing Company, http://www.tsmc.com/english/default.htm. [33] The patterning prediction simulation works - Sentaurus Lithography (e-beam), http://www.synopsys.com/. [34] E. Pargon, M. Martin, J. Thiault, O. Joubert, J. Foucher, and T. Lill, “Linewidth roughness transfer measured by critical dimension atomic force microscopy during plasma patterning of polysilicon gate transistors”, J. Vac. Sci. Technol. B, vol. 26, pp. 1011-1120, June 2008. [35] SEMI, “ Specification for metrology pattern cells for integrated circuit manufacture”, Standard SEMI, pp. 19-92, 1996. [36] Neil R. Wilson and Julie V. Macpherson. “Carbon nanotube tips for atomic force microscopy”, Nat Nano, vol. 4, pp. 483-491, July 2009. [37] M. J. Wieland, G. d. Boer, G.F. ten Berge, M. v. Kervinck, R. Jager, J. J. M. Peijster, E. Slot, S. W. H. K. Steenbrink, T. F. Teepen, and B. J. Kampherbeek, “MAPPER: High throughput maskless lithography”, SPIE Proc., vol. 7637, no. 76370F, July 2010. [38] W. J. Dressick, M.-S. Chen, S. L. Brandow, K. W. Rhee, L. M. Shirey, and F. K. Perkins, “Imaging layers for 50 kV electron beam lithography: Selective displacement of noncovalently bound amine ligands from a siloxane host film”, Appl. Phys. Lett., vol. 78, pp. 676-678, Jan. 2001. [39] S. H. Yang, C. C. Wang, “Domestic Indirect Feedback Compensation of Multiple-Stage Amplifiers for Multiple-Voltage Level-Converting Amplification”, Proc. ICICDT, pp. 1-4, May 2011. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63657 | - |
| dc.description.abstract | 在這樣一個微影技術迅速攀升的時代，由於電子束直寫（EBDW）微影系統解析度高、又無需光罩，便因此成為次世代的主流之一，但卻有著低曝寫速度之問題，於是曾有研究提出，利用大量的電子束所形成的多重電子束直寫（MEBDW）微影系統進而提升其曝寫的速度，也以多重電子束直寫微影系統裡的電子束驅動電路，控制一單閘極層的電子光學系統（EOS），進而調節電子光學系統之發射電流。然而，傳統的驅動電路設計只考慮到訊號品質（SF），也以實際電路以及其中包含很多變數之電路模擬，如電晶體長度和寬度，進而修正驅動電路的設計，使得傳統設計方式不僅未考慮微影之特性和曝寫速度的最佳化，在修正設計方面則更是耗時。因此提出一藉由轉移函數調整具有考慮微影特性之電子束微影曝光控制電路（ECC）最佳化曝寫速度之方法。此方法不僅於最佳化曝寫速度時考慮了微影品質（PF），更因電路部分被替換為轉移函數的型態，予以簡化曝寫速度在最佳化時所需調整的變數，更大幅降低最佳化所需耗費的時間。由結果可得知，不僅曝寫速度有著顯著的提高，更經由比對工業技術研究社 (ITRS) 當中21納米節點的規格，於各個微影結果上的線寬以及光阻厚度更是較於符合。 | zh_TW |
| dc.description.abstract | Electron-beam-direct-write lithography is one of the promising candidates for next-generation lithography because of its ability of high resolution and maskless operation. Its issue of low throughput is improved by multiple-electron-beam-direct-write lithography. The emission current of an electron optical system (EOS) is controlled to decide whether the resist is developed because of relationship between it and the dose. Thus exposure control circuit (ECC) has been proposed for adjusting the emission current of an EOS. In the traditional design of ECC, a lot of variables are adjusted for meeting the requirement of signal fidelity (SF). It is verified by circuit simulation and experiments with the actual circuit. However, it lacks for throughput optimization. The patterning fidelity (PF) is not necessarily acceptable because the exposure results are verified after ECC design. In this work, a new method of ECC response optimization for improving throughput of electron beam lithography considering PF is proposed. The PF is considered for optimizing the throughput. Preliminary results indicate that the throughput is significantly improved, while theses resist profiles are met the International Technology Roadmap of Semiconductors requirements. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T17:15:48Z (GMT). No. of bitstreams: 1 ntu-101-R99921010-1.pdf: 1162991 bytes, checksum: 079586b66d3411f467a09eac7dcf66a7 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | Abstract i
摘要 ii Statement of Contributions iii 誌謝 iv Table of Contents v List of Figures vi List of Tables vii I. INTRODUCTION 1 II. EXPOSURE CONTROL CIRCUIT DESIGN FLOW 3 III. CONSIDERATIONS OF PATTERNING PREDICTION SIMULATION 5 A. Transformation from drawn layout to digital voltage signal 5 B. Electron optical system architecture 5 C. Circuit model of electron optical system extraction 8 D. Define exposure control circuit with electron optical system 11 IV. PATTERNING PREDICTION SIMULATION FLOW 14 V. RESULTS AND DISCUSSION 17 A. Optimal throughput of conjectured exposure control circuit design 17 B. Optimal throughput of the new exposure control circuit design 24 VI. CONCLUSION AND FUTURE WORK 28 REFERENCE 28 | |
| dc.language.iso | en | |
| dc.subject | 微影品質 | zh_TW |
| dc.subject | 多重電子束直寫 | zh_TW |
| dc.subject | 曝光控制電路 | zh_TW |
| dc.subject | 電子光學系統 | zh_TW |
| dc.subject | 訊號品質 | zh_TW |
| dc.subject | 電子束直寫 | zh_TW |
| dc.subject | 最佳化 | zh_TW |
| dc.subject | Electron optical systems | en |
| dc.subject | Patterning fidelity | en |
| dc.subject | Signal fidelity | en |
| dc.subject | Exposure control circuits | en |
| dc.subject | Optimization | en |
| dc.subject | Multiple-electron-beam-direct-write | en |
| dc.subject | Electron-beam-direct-write | en |
| dc.title | 考慮微影特性於曝光控制電路響應最佳化進而改善電子束微影曝寫速度之方法 | zh_TW |
| dc.title | Exposure control circuit response optimization method for improving throughput of electron beam lithography considering patterning fidelity | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳政宏(Jeng-Horng Chen),顏家鈺(Jia-Yush Yen),李佳翰(Jia-Han Li) | |
| dc.subject.keyword | 電子束直寫,多重電子束直寫,電子光學系統,曝光控制電路,訊號品質,微影品質,最佳化, | zh_TW |
| dc.subject.keyword | Electron-beam-direct-write,Multiple-electron-beam-direct-write,Electron optical systems,Exposure control circuits,Signal fidelity,Patterning fidelity,Optimization, | en |
| dc.relation.page | 33 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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