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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳瑞北 | |
| dc.contributor.author | Ming-Chung Wu | en |
| dc.contributor.author | 吳旻鍾 | zh_TW |
| dc.date.accessioned | 2021-06-16T16:37:23Z | - |
| dc.date.available | 2012-11-22 | |
| dc.date.copyright | 2012-11-22 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-10-07 | |
| dc.identifier.citation | [1]P. Bai, “Advancing Moore’s Law: Challenges and Opportunities,” in IEEE 8th International Conference, on ASICON, Changsha, Hunan, China, Oct. 20-23, 2009, pp. 7-8.
[2]Chris A. Mack, “Fifty Years of Moore’s Law,” IEEE Trans. Semiconductor Manufacturing, vol. 24, no. 2, pp. 202-207, May 2011. [3]Kelin J. Kuhn, “Moore’s Law Past 32nm: Future Challenges in Device Scaling,” in International Workshop on Computational Electronics, Milwaukee, Wisconsin, USA, May 22-25, 2009. [4]Chang Liu and Sung Kyu Lim, “A Study of Signal Integrity Issues in Through-Silicon-Via-based 3D ICs,” in International Interconnect Technology Conference, San Francisco, California, USA, June 7-9, 2010. [5]C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, “High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging,” in Electronics Systeminegration Technology Conference, Dresden, Germany, Sept. 5-7, 2006, vol. 1, pp. 215-220. [6]J. S. Pak, J. Cho, J. Kim, J. Lee, H. Lee, K. Park, and J. Kim, “Slow Wave and Dielectric Quasi-TEM Modes of Metal-Insulator-Semiconductor (MIS) Structure Through Silicon via (TSV) in Signal Propagation and Power Delivery in 3D Chip Package,” in IEEE 60th Electron. Comp. Tech. Conf., Las Vegas, Nevada, USA, June 1-4, 2010, pp. 667-672. [7]J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M.-S. Suh, K.-Y. Byun, and J. Kim, “High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV),” IEEE Trans. Components, Packaging and Manufacturing Technology, vol. 1, no. 2, pp. 181-195, Feb. 2011. [8]R.-B. Sun, C.-Y. Wen, and R.-B. Wu, “RC passive equalizer for through silicon via,” in IEEE 19th Electrical Performance Electron. Packag. Syst., Austin, Texas, USA, Oct. 25-27, 2010, pp. 45-48. [9]J. Kim, E. Song, J. Cho, J. S. Pak, J. Lee, H. Lee, K. Park, and J. Kim, “Through Silicon Via (TSV) Equalizer,” in IEEE 18th Electrical Performance Electron. Packag. Syst., Portland/Tigard, Oregon, USA, Oct. 19-21, 2009, pp. 13-16. [10]J. S. Pak, J. Kim, J. Cho, K. Kim, T. Song, S. Ahn, J. Lee, H. Lee, K. Park, and J. Kim, “PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models,” IEEE Trans. Comp. Packag. Manuf. Technol., vol. 1, no. 2, pp. 208-219, Feb. 2011. [11]R.-B Wu, “Resistance Modeling of Periodically Perforated Mesh Planes in Multilayer Packaging Structures,” IEEE Trans. Comp. Hybrids, Manuf. Technol., vol. 12, no. 3 , pp. 365~372, Sep. 1989. [12]S. H. Hall and H. L. Heck, Advanced Signal Integrity for High-Speed Digital Designs, John Wiley & Sons, 2009. [13]S. Lin and N. Chang, “Challenge in Power-Ground Integrity,” in IEEE/ACM Int’l Conf. Computer Aided Design, San Jose, California, USA, Nov. 4-8, 2001, pp. 644-651. [14]J. M. Williamson, M. S. Nakhla, Q. J. Zhang, and P. D. van der Puije, “Ground Noise Minimization in Integrated Circuit Packages through Pin Assignment Optimization,” IEEE Trans. Comp. Packag. Manufact., Technol. B, vol. 19, no. 2, pp. 361-371, May 1996. [15]R.-B. Sun, C.-M.. Lin, and R.-B. Wu, “Designs of Signal-Ground Bump-Patterns for Minimizing the Simultaneous Switching Noises in a Ball Grid Array,” in IEEE 17th Electrical Performance Electron. Packag,, San Jose, California, USA, Oct. 27-29, 2008, pp. 15-18. [16]J. U. Knickerbocker et al., “3-D Silicon Integration and Silicon Packaging Technology Using Silicon through-Vias,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 15-18, ???, 20??. [17]M. Popvich, A. V. Mezhiba, and E. G. Friedman, Power Distribution Networks with On-chip Decouploing Capacitors. New York, USA: Springer, 2008, Chapter 1. [18]Y. Xu, W. Liu, Y. Wang, J. Wu, X. Chen, and H. Yang, “On-Line MPSOC Scheduling Considering Power-Gating Induced Power/Ground Noise,” in IEEE Computer Society Annual Symposium VLSI, Tampa, Florida, USA, May 13-15, 2009, pp. 109-114. [19]J. Kim, J. Shim, J. S. Pak, and J. Kim, “Modeling of Chip-Package-PCB Hierarchical Power Distribution Network Based on Segmentation Method,” in IEEE Electrical Design Adv. Packag. Systems, Seoul, Korea, Dec, 10-12, 2008, pp. 85-88. [20]L.R. Zheng and H. Tenhunen, “Fast Modeling of Core Switching Noise on Distributed LRC Power Grid in ULSI Circuits,” IEEE Trans. Adv. Packag., vol.24, no. 8, pp. 245-254, Aug. 2001. [21]W. Ahmad, Q. Chen, L. R. Zheng, and H. Tenhunen, “Peak-to-Peak Switching Noise and LC Resonance on a Power Distribution TSV Pair,” in IEEE 19th Electron. Package. Syst., Austin, Texas, USA, Oct. 25-27, 2010, pp. 173-176. [22]W. Ahmad, L. R. Zheng, R. Weerasekera, Q. Chen, A. Y. Weldezion, and H. Tenhunen, “Power Integrity Optimization of 3D Chips Stacked through TSVs,” in IEEE 18th Electrical Performance Electron. Packag. Syst., Portland, Oregon, USA, Oct. 19-21, 2009, pp. 105-108. [23]K. Kim, W. Lee, T. Song, J. Kim, J. S. Pak, J. Kim, H. Lee, Y. Kwon, and K. Park, “Analysis of Power Distribution Network in TSV-Based 3D-IC,” in IEEE 19th Electrical Performance Electron. Packag. Syst., Austin, Texas, USA, Oct. 25-27, 2010, pp. 177-180. [24]鄭翔元，三維晶片中同時切換雜訊最小化的直通矽晶連通柱擺置設計， 國立台灣大學碩士論文，2011年6月。 [25]MATLAB, The Math Works, Inc. [Online]. Available: http://www.mathworks.com [26]D. K. Cheng, Field and Wave Electromagnetics , 2nd ed. Addison Wesley, 1989. [27]A. V. Oppenheim, A. S. Willsky, and S. H. Nawab, Signal and Systems, 2nd ed., Wiley, 2003. [28]R. R. Tummala and M. Swaminathan, Introduction to System-On-Package (SOP), McGraw-Hill, Inc., 2008, Chap 3. [29]Q3D Extractor, Version 6, Ansys, Inc. [Online]. Available: http://www.ansys.com [30]U. Kang et al., “8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology,” IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 111-119, Jan. 2010. [31]E. B. Rosa, “The Self and Mutual Inductance of Linear Conductors,” Bulletin of the National Bureau of Standards, vol. 4, no. 2, pp. 301-344, 1908. [32]F. W. Grover, Inductance Calculations: Working Formulas and Tables. Mineola, New York, USA: Dover Publications, 2009. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63367 | - |
| dc.description.abstract | 隨著高速數位電路的設計趨勢朝向高頻率操作，高功率密度，低功率消耗及體積更小，因此維持電路系統的訊號完整度和電源完整度成為設計上的一大挑戰，而串音及同時切換雜訊的產生造成訊號傳輸品質的不良及電源供應穩定的問題，影響電路運作的表現。
本論文使用傅立葉轉換快速建立三維晶片內直通矽晶連通柱陣列的等效簡化電路模型。直通矽晶連通柱在晶片中扮演訊號/電源/接地其中之一的功能，若將每一根直通矽晶連通柱與其它根直通矽晶連通柱彼此間的耦合效應皆納入考慮，對建立等效電路及電路分析都將相當耗時。而耦合效應隨著距離衰減，當距離大到達某一程度時，耦合效應將衰減到可忽略的程度，因此根據此一隨距離衰減的特性，對多根直通矽晶連通柱建立簡化的等效電路模型，進而分析在任意訊號/電源/接地擺置的情況下，直通矽晶連通柱陣列間的串音及計算同時切換雜訊峰值，藉以達到簡化電路預測的目的。 | zh_TW |
| dc.description.abstract | With the design trends of high clock frequencies, high power density, low voltage levels, and small size in the development of the high-speed digital systems. the issues of crosstalk and simultaneous switching noise (SSN) in the high-speed digital systems are getting more and more important.
In this paper, a design methodology based on the two--dimensional Fourier transform is proposed to attain a simplified through-silicon via (TSV) equivalent circuit. TSVs may be assigned to be the signal/ground/power net in a chip and there are the coupling effects between any of two TSVs. It is time-consuming to attain an equivalent circuit for analyzing the circuit by the traditional methods because all the coupling effects between any of two TSVs are considered. To improving this problem, the distance decay characteristic of coupling effects is considered in attaining the equivalent circuits. By ignoring the coupling effects between two TSVs with the far enough distance can be ignored, a simplified equivalent circuit can be attained. With the proposed simplified equivalent circuit, the crosstalk and SSN in a chip, whose TSVs are randomly assigned with the signal/ground/power ratios state, can be estimated. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T16:37:23Z (GMT). No. of bitstreams: 1 ntu-101-R99942092-1.pdf: 1741682 bytes, checksum: dcc26607caf1881c83d55fcc16e725fc (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 摘要 iii 目錄 vii 圖目錄 ix 表目錄…………………………………………… ……………………………….…xii 第一章 緒論 1 1.1 研究動機 1 1.2 文獻探討 3 1.3 章節內容概述 12 1.4 貢獻 15 第二章 基礎理論 7 2.1 傳輸線理論 7 2.2 傅立葉級數及轉換 9 2.3 串音 12 2.4 同時切換雜訊 15 第三章 直通矽晶連通柱簡化模型及串音分析 18 3.1直通矽晶連通柱特性 18 3.2以傅立葉轉換建立直通矽晶連通柱陣列簡化等效模型 20 3.3任意訊號/接地擺置直通矽晶連通柱之串音分析 288 第四章 同時切換雜訊分析 47 4.1晶片電源傳輸網路 47 4.2電源傳輸網格與直通矽晶連通柱陣列的電感矩陣結合 53 4.3訊號/接地/電源擺置的同時切換雜訊估算 55 第五章 結論 …………………………………………………………………………..63 參考文獻……………. 64 | |
| dc.language.iso | zh-TW | |
| dc.subject | 串音 | zh_TW |
| dc.subject | 直通矽晶連通柱 | zh_TW |
| dc.subject | 同時切換雜訊 | zh_TW |
| dc.subject | 傅立葉轉換 | zh_TW |
| dc.subject | Fourier transform | en |
| dc.subject | simultaneous switching noise(SSN) through-silicon via (TSV) | en |
| dc.subject | Terms-Crosstalk | en |
| dc.title | 任意訊號與接地擺置直通矽晶連通柱陣列之簡化模型建立及電氣特性分析 | zh_TW |
| dc.title | A Simplified Modeling and Electrical Characteristic Analysis for TSV Arrays with Arbitrary Signal and Ground Assignments | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳宗霖,洪子聖,林建民,林丁丙 | |
| dc.subject.keyword | 串音,傅立葉轉換,同時切換雜訊,直通矽晶連通柱, | zh_TW |
| dc.subject.keyword | Terms-Crosstalk,Fourier transform,simultaneous switching noise(SSN) through-silicon via (TSV), | en |
| dc.relation.page | 66 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-10-09 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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