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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63334
標題: | 基於條件機率之離群路徑偵測技術 A Conditional Probability Based Outlier Path Detection Technique |
作者: | Li-Jen Hu 胡立人 |
指導教授: | 黃俊郎 |
關鍵字: | 測試, testing, |
出版年 : | 2012 |
學位: | 碩士 |
摘要: | 隨著製程技術的演進,積體電路設計進入奈米時代,在元件越做越小電路的執行速度卻越做越快的同時,製程飄移(process variation) 對於電路的影響越來越顯著,進而造成良率降低。這是因為原本的clock cycle比較長,所以小的variation對於整個電路的效能並不會有重大的影響,然而現今的電路的clock cycle變的非常小,所以製程飄移所帶來的效應變得非常重要。因此,在分析電路時,把製程飄移考慮進去已經變成相當重要的議題。
我們用[27]中所提到的variation model來定義outlier path,在[27]中假設path delay variation是受到path之間的距離所影響,舉例來說,越接近的兩條path越容易受到同一錯誤所影響,因此他們的相關性也越高,如果有某條path違反了這個variation model,那我們會把這條path視為outlier path。在本論文中,我們提出了一個實驗流程去檢測outlier path,這個實驗流程是用條件機率的方式去判定我們所檢測的path是否為outlier path,主要的想法是用path之間的相關性去判斷哪些path是outlier path,以這個實驗流程檢測到outlier path的準確度達到90%以上。 Because of the improvement of manufacturing techniques, the designers define tighter timing specification than before. The clock cycle becomes smaller and smaller. Therefore, process variation has more effect on path delay, and it may cause the chip to fail. How to model the process variation when analyzing a circuit becomes an important issue in recent years. In this thesis, we use the variation model [26] to define an outlier path. In [26], it assumes that gate delay variations are determined by the distance between gates. The closer two gates are, the higher correlation they will have. Based on the correlation model, we can derive the path delays and correlations from gate delays and correlations. If paths do not follow the variation model, they will be defined as outlier paths. Then, we proposed an experimental flow to detect the outlier paths in chip. The proposed flow is based on the conditional probability formula to deal with the path correlation’s problem. In other words, we will use the correlation between paths to justify which one is outlier path. The accuracy of outlier detection is higher than 90%. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63334 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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