一個具有自適應注入鎖定技術之0.5V Sub-GHz鎖相迴路應用於物聯網領域

Abstract

近年來，5G通訊蓬勃發展，隨著製程及物聯網技術的不斷進步，穿戴式裝置、IoT晶片與生醫晶片應用也越來興起。然而，產品也越來越注重在小面積，長生命週期的趨勢，各項電子產品的生命週期皆受限於電池的壽命長短，因此低功耗的設計越顯得更加重要。 隨著物聯網與製程的不斷進步及網路通訊協定的制定，產業界在NB-IoT、LTE-M晶片布局與穿戴式裝置的應用也越發興起，由於頻段的壅塞使得全球5G通訊協定有將近50%設立在Sub-GHz下的頻段。根據國際半導體科技組織的報告指出，下一世代低功耗電路設計，其供應電壓將下降至0.5V以下，因此本篇電路設計將應用在0.5電壓伏特且Sub-GHz的規格下。在積體電路系統中，鎖相迴路負責提供參考頻率，但是在低電壓的環境下，電晶體的電流會降低至數十微安培，微弱的電流導致鎖相迴路的操作頻率受到限制。除此之外，低電壓的環境也意味著雜訊效應會變得更加明顯，進而使得電路表現明顯變差。 本論文提出改善及討論的方法以克服低電壓架構的限制。晶片採用TSMC 90nm標準CMOS製程實現，晶片面積和核心面積分別為0.570mm2 和 0.065mm2。我們提出了一個操作在供應電壓0.5伏特的自動注入鎖定之鎖相迴路，鎖定頻率為870MHz至1310MHz。當操作頻率鎖定在Sub-GHz時並且開啟自動注入的狀態下，位移1MHz的相位雜訊為 -101dBc/Hz，積分範圍從1kHz到30MHz的方均根抖動量為5.33ps，參考突波為 -41.2dB，功率消耗為362.6μW。 在供應電壓0.5伏特及低功耗的條件下，我們將採用改良式之Bootstrapped 技術來提升震盪器的操作頻率。差動對Bootstrapped技術可以增加震盪器輸出訊號的震幅進而增加電晶體驅動電流的能力，差動的架構也會有效地消除低壓下的雜訊影響。另外，改良的CP克服了電壓的限制也有效地降低參考突波。針對相位雜訊的問題，我們採用了次諧波注入鎖定的技術來抑制震盪器的相位雜訊和抖動。我們的設計為全自動注入鎖定。

In recent years, 5G communication industry develops faster and faster. Based on the advance of the integrated circuit technologies, applications of 5G communication IC, biomedical IC and wearable medical devices become more popular. However, the issue of chip area and long life cycle product is more popular. The life cycle of eletronic product is limited by the power consumption, which focus on the battery effeciency. Thus, the low power design for circuits are more important. With the advance of IoT communication and Network protocol, chips for NB-IoT and LTE-M application become more popular. Owing to the congestion of the Network frequency band, there is 50% of Network protocol setting at sub-GHz bands. According to the reports proposed by International Technology Roadmap for Semiconductor (ITRS), supply voltage of general low-power circuits will be scaled down to 0.5V for the next generation applications. Thus, our circuit design is applicated for 0.5V supply voltage and sub-GHz bands. In the integrated-circuit system, the phase-locked loop is responsible for providing the reference frequency. However, the current of transistors is much weaker in low-voltage environment which limits the operating frequency of the phase-locked loop. Otherwise, in low-voltage environment, the noise effect might become more severe, that lead to a worse performance. In this thesis, we proposed an improved solution to the above topics. The proposed circuit is a 0.5V phase-locked loop with adaptive injection-locked technique. The chip is fabricated in TSMC 90nm Standard CMOS Technology. The chip area and active core area are 0.570mm2 and 0.065mm2, respectively. The tuning range of the proposed circuit is from 870 to 1310MHz. At the output clock of 1024MHz, the measured spur level at 32MHz away from the 1024MHz clock output is -41.2dB. The measured phase noise at 1MHz offset is -101dBc/Hz and the measured rms jitter integrated from 1kHz to 30MHz is 5.33ps with adaptive injection locking. The power consumption of the fabricated circuit is 362.6μW, which is lower than general requirements. The modified bootstrapped technique is adopted to increase the frequency of oscillator under low supply voltage of 0.5V. The swing of oscillator and the driving ability of MOSFET can be increased by using the differential bootstrapped technique. The modified gate switching charge pump (CP) not only overcome the voltage limit but also reduce the reference spur. The injection technique is adopted to suppress the phase noise and jitter of PLL output clock. Besides, this work is realized with adaptive injection techniques.