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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63236完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳家麟(Ja-Ling Wu) | |
| dc.contributor.author | Yun-Chung Shen | en |
| dc.contributor.author | 沈允中 | zh_TW |
| dc.date.accessioned | 2021-06-16T16:29:52Z | - |
| dc.date.available | 2014-01-16 | |
| dc.date.copyright | 2013-01-16 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-12-27 | |
| dc.identifier.citation | [1] SLEPIAN, D. AND WOLF, J. 1973. Noiseless coding of correlated information
sources. IEEE Trans. Inf. Theory, 19, 4, 471-480. [2] WYNER, A. AND ZIV, J. 1976. The rate-distortion function for source coding with side information at the decoder. IEEE Trans. Inf. Theory, 22, 1, 1-10. [3] ARON, A., ZHANG, R., AND GIROD, B. 2002. Wyner-Ziv coding of motion video. The Asilomar Conf. on Signals, Systems and Computers, 240-244. [4] GIROD, B., ARON, A., RANE, S., AND REBOLLO-MONEDERO, D. 2005. Distributed video coding. In Proc. IEEE, 71-83. [5] ARTIGAS, X., ASCENSO, J., DALAI, M., KLOMP, S., KUBASOV, S., AND OUARET, M. 2007. The DISCOVER codec: architecture, techniques and evaluation. Picture Coding Symposium. [6] VARODAYAN, D., CHEN, D., FLIERL, M., AND GIROD, B. 2008. Wyner-Ziv coding of video with unsupervised motion vector learning. EURASIP Signal Processing: Image Communication, 23, 5, 369-378. [7] MARTINS, R., BRITES, C., ASCENSO, J., AND PEREIRA, F. 2009. Refining side information for improved transform domain Wyner-Ziv video coding. IEEE Trans. Circuits Syst. Video Technol. 19, 9, 1327-1341. [8] MARTINS, R., BRITES, C., ASCENSO, J., AND PEREIRA, F. 2010. Statistical motion learning for improved transform domain Wyner-Ziv video coding. IET Image Processing, 4, 1, 28-41. [9] MARTINEZ, J.L., KALVA, H., FERNANDEZ-ESCRIBANO, G.,FERNANDO, W.A.C., AND CUENCA, P. 2009. Wyner-Ziv to H.264 video transcoder. IEEE International Conf. on Image Processing, 2941-2944. [10] BRITES, C., ASCENSO, J., PEDRO, J., AND PEREIRA, F.2008. Evaluating a feedback channel based transform domain Wyner-Ziv video codec. EURASIP Signal Processing: Image Communication, 23, 4, 269-297. 89 [11] VARODAYAN, D., AARON, A., AND GIROD, B. 2006. Rate-adaptive codes for distributed source coding. EURASIP Signal Processing Journal, Special Section on Distributed Source Coding, 86, 11. [12] ISO/IEC 14496-10 2003. Coding of audio-visual objects–part 10: advanced video coding (July 2003, 1st edn; also ITU-T: 2003, H.264). [13] ASCENSO, J., BRITES, C., AND PEREIRA, F. 2007. Content adaptive Wyner-Ziv video coding driven by motion activity. IEEE International Conf. on Image Processing. [14] KLOMP, S., VATIS, Y., AND OSTERMANN, J. 2006. Side information interpolation with sub-pel motion compensation for Wyner-Ziv decoder. International Conf. on Signal Processing and Multimedia Applications. [15] BRITES, C. AND PEREIRA, F. 2008. Correlation noise modeling for efficient pixel and transform domain Wyner-Ziv video coding. IEEE Trans. Circuits Syst. Video Technol. 18, 9, 1177-1190. [16] WESTERLAKEN, R.P., BORCHERT, S., KLEIN GUNNEWIEK, R., AND LAGENDIJK, R.L. 2007. Analyzing symbol and bit plane-based LDPC in distributed video coding. IEEE International Conf. on Image Processing, II 17-20. [17] CHENG, S. AND XIONG, Z. 2005. Successive refinementfor the Wyner-Ziv problem and layered code design. IEEE Trans. on Signal Processing, 53, 8, 3269-3281. [18] KUBASOV, D., NAYAK, J., AND GUILLEMOT, C. 2007. Optimal reconstruction in Wyner-Ziv video coding with multiple side information. IEEE Workshop on Multimedia Signal Processing. [19] ESMAILI, G. AND COSMAN, P. 2009. Low complexity spatio-temporal key frame encoding for Wyner-Ziv video coding. Data Compression Conference, 382-390. [20] CHIOU, B.-R., SHEN, Y.-C., CHENG, H.-P., AND WU, J.-L. 2010. Performance improvement of distributed video coding by using block mode selection. ACM International Conf. on Multimedia. [21] BRITES, C. AND PEREIRA, F. 2007. Encoder rate control for transform domain Wyner-Ziv video coding. IEEE International Conf. onImage Processing. 90 [22] LIST, P., JOCH, A., LAINEMA, J., BJØNTEGAARD, G., AND KARCZEWICZ, M. 2003. Adaptive deblocking filter. IEEE Trans. Circuits Syst. Video Technol. 13, 7, 614 – 619. [23] NVIDIA DEVELOPER - http://developer.nvidia.com/object/cuda.html. [24] OPENMP. 2008. OpenMP Complete Specifications Version 3.0. [25] H.264 REFERENCE SOFTWARE - http://iphome.hhi.de/suehring/tml. [26] MARK HARRIS. 2007. Optimizing parallel reduction inCUDA. NVIDIA Developer Technology. [27] PAI, Y.-S., CHENG, H.-P., SHEN, Y.-C., AND WU, J.-L. 2010. Fast decoding for LDPC based distributed video coding. ACM International Conf. on Multimedia. [28] LIVERIS, A., XIONG, Z., AND GEORGHIADES, C. 2002. Compression of binary sources with side information at the decoderusing LDPC codes. IEEE Commun. Lett., 6, 10, 440-442. [29] TEST CONDITION OF DISCOVER CODEC- http://www.img.lx.it.pt/~discover/test_conditions.html. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63236 | - |
| dc.description.abstract | 分散式視訊編碼的發展是未來相當具有指標性的編碼壓縮技術，也是消息理
論在學術發展上的重要里程碑，無論在業界、學術界都相當重視這部分的發展及 研究。分散式視訊編碼技術跟傳統視訊壓縮技術最大的差別在於分散式視訊編碼 可以有彈性地把壓縮編碼的計算負擔分散給解壓縮端，根據資訊理論的證明，分 散式視訊編碼的壓縮編碼效能，理論上等同於傳統視訊編碼，這個新的技術在多 端點分散式異質系統視訊通訊環境下具有相當的潛力。本論文「分散式視訊編碼 之旁資訊增強與平行化設計，以提昇新世代分散式視訊壓縮應用為目標，共分成 兩大方向：解壓縮端附帶消息位元生成演算法與解壓縮端演算法平行化。分別從 解壓縮端的演算法設計以及藉由通用圖形處理器平行加速運算兩方面著手，適切 地符合使用者對於新世代分散式視訊壓縮應用的需求。 解壓縮端附帶消息位元生成演算法之主要目的是對於由動態預測與動態補償 的高複雜度處理程序設計了空間域冗餘消除的技術， 分散式視訊編碼將傳統資料 壓縮的計算負擔由編壓縮端移至解壓縮端，符合在傳送端編碼器的低功率要求， 可有效降低編碼硬體成本，但是在壓縮效率上卻離理論值還有一段的差距，故本 論文在壓縮端的演算法設計主要著重於研發新一代的附帶消息位元生成的技術， 以有效提升附帶消息的產生，俾使分散式視訊編碼的壓縮效率能符合實際應用的 要求。 解壓縮端演算法平行化之主要目的是為達到資訊理論的通道極限，低密度同 位檢查碼的分組碼長度必須要夠大，所以節點的數目將非常龐大，在中央處理器 上計算所對應的機率參數會耗上大量的時間，因此，我們將把低密度同位檢查碼 中最花時間的解碼部份，實作在通用圖形處理器上，利用通用圖形處理器內眾多 的算術邏輯單元來達成平行計算的效果，將解壓縮的時間大幅度的降低，以符合 實際上應用及時解碼的需求。 | zh_TW |
| dc.description.abstract | Despite gaining certain improvements in coding performances recently, the
effectiveness (in terms of rate-distortion) and theefficiency (in terms of decoding speed) of the existing Wyner-Ziv (WZ) codecs are far behind that of the state-of-the-art prediction-based video coding standards. In other words, for decades, the poor RD performance and the high coding delay hinder WZ codecs from being applied to practical applications. To respond to the above challenges, an effective and efficient WZ video coding architecture, referred to herein as“Improved Side Information and Parallelized Design” (ISIPaD) for distributed videocoding (DVC), is proposed and realized to enhance the RD performance and the execution speed at the same time. Due to the difference of main focus, we present our work in a series of two parts. Part I of this work details the proposed coding scheme and shows its RD superiority over the related works, while Part II addresses the parallelizability of the proposed coding architecture and shows its timing performance we obtained when ISIPaD is realized on a multi-core CPU-plus-GPGPU platform. With much enhanced performances in both rate distortion (up to 3.6dB in RD measures) and execution time (60.97 times faster in speed), as compared with those of the state-of-the-art WZ video codecs, our work demonstrates a great potential for DVC being applied to real applications in the near future. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T16:29:52Z (GMT). No. of bitstreams: 1 ntu-101-D96944004-1.pdf: 3489493 bytes, checksum: cf02cc4f1b789e45e5014565d8985b91 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 口試委員會審定書................................................................................................................................ II
誌謝...................................................................................................................................................... III 摘要..................................................................................................................................................... IV ABSTRACT ............................................................................................................................................. V LIST OF FIGURES ....................................................................................................................................IX LIST OF TABLES ......................................................................................................................................XI CHAPTER 1 INTRODUCTION ............................................................................................................... 1 CHAPTER 2 BASELINE WZ CODEC ....................................................................................................... 5 2.1 BASELINE ENCODING PROCESS.......................................................................................................... 7 2.1.1 WZ and Key Frame Splitting .................................................................................................. 7 2.1.2 Transform and Quantization ................................................................................................ 7 2.1.3 Channel Encoder and Buffer ................................................................................................. 8 2.2 BASELINE DECODING PROCESS.......................................................................................................... 9 2.2.1 Side Information Creation ..................................................................................................... 9 2.2.2 Correlation Noise Parameter Estimation ............................................................................ 12 2.2.3 Correlation Noise Distribution Modeling ............................................................................ 13 2.2.4 Conditional Bit Probabilities Computation.......................................................................... 15 2.2.5 Minimum Rate Estimation (MRE) ....................................................................................... 16 2.2.6 Channel Decoder and Decoder Success/Failure .................................................................. 17 2.2.7 Reconstruction and Inverse Transform ............................................................................... 17 2.2.8 Statistic Motion Field (SMF) Probabilities Updating........................................................... 18 2.2.9 Side Information Re-Estimation .......................................................................................... 19 CHAPTER 3 ISIPAD CODEC ................................................................................................................ 20 3.1 RE-CREATION MODULE OF SIDE INFORMATION.................................................................................. 21 3.2 BLOCK MODE SELECTION MODULE.................................................................................................. 22 3.2.1 Skip Mode Selection ............................................................................................................ 23 3.2.2 Intra Mode Selection ........................................................................................................... 24 3.2.3 Effect of Block Mode Selection Module .............................................................................. 25 3.3 ADAPTIVE DEBLOCKING FILTER MODULE........................................................................................... 26 CHAPTER 4 PARALLELIZING ISIPAD DECODER ................................................................................... 28 4.1 PROGRAMMING AND EXECUTION MODEL OF CUDA ........................................................................... 28 4.2 PARALLEL SIDE INFORMATION CREATION.......................................................................................... 30 4.2.1 Parallelizing the FIR Filtering on Multi-Core CPU ................................................................ 30 4.2.2 Parallelizing the Forward Motion Estimation on GPGPU .................................................... 31 4.3 PARALLEL CORRELATION NOISE MODELING....................................................................................... 34 4.3.1 Parallelizing the Correlation Noise Modeling Distribution on GPGPU ................................ 34 4.3.2 Parallelizing the Conditional Bit Probabilities Computation on GPGPU ............................. 36 4.4 PARALLEL LDPCA DECODING......................................................................................................... 37 4.4.1 The LDPCA Codes ................................................................................................................ 37 4.4.2 The Message-Passing Algorithm ......................................................................................... 41 4.4.3 Accumulated Parity Check matrix and Rate Adaptivityof LDPCA codes ............................. 43 4.4.4 Acceleration of LDPCA Decoding in DVC ............................................................................. 47 4.4.5 GPGPU Architecture and Programming Model .................................................................. 48 4.4.6 Parallel LDPCA Decoding on GPGPU ................................................................................... 51 4.4.7 The Data Parallel Algorithm of LDPCA Decoding on GPGPU Platform ................................ 55 4.4.8 Ladder Step Size Request (LSSR) .......................................................................................... 56 4.5 PARALLEL SIDE INFORMATION RE-CREATION..................................................................................... 58 4.6 PARALLEL STATISTIC MOTION LEARNING........................................................................................... 59 4.6.1 Parallelizing the Statistic Motion Field Probabilities Updating on GPGPU ......................... 59 4.6.2 Parallelizing the Side Information Re-Estimation onMulti-Core CPU ................................. 61 CHAPTER 5 PERFORMANCE EVALUATIONS ....................................................................................... 62 5.1 EXPERIMENTAL SETTINGS............................................................................................................... 62 5.1.1 Test conditions for RD performance .................................................................................... 62 5.1.2 Test Conditions for Decoding Speed .................................................................................... 63 5.1.3 Benchmarks for Evaluating ISIPaD Codec ........................................................................... 64 5.2 RDPERFORMANCE....................................................................................................................... 67 5.2.1 ISIPaD Video Codec against Other WZ Video Codecs .......................................................... 67 5.2.2 ISIPaD Video Codec against Standard Video Codecs ........................................................... 68 5.3 DECODING SPEED......................................................................................................................... 68 5.3.1 The Bottlenecks of WZ Decoding Time................................................................................ 69 5.3.2 ISIPaD Decoder against Other WZ Decoders ....................................................................... 72 5.3.3 Effectiveness of Proposed Parallelizing Techniques for ISIPaD Decoder ............................. 73 5.3.4 Complexity of ISIPaD Encoder ............................................................................................. 75 CHAPTER 6 THE PROPOSED SIDE INFORMATION REFINEMENT FRAMEWORK .................................. 76 6.1 CANDIDATE BLOCK SELECTION......................................................................................................... 77 6.1.1 Block Reconstruction ........................................................................................................... 77 6.1.2 Error Computation(Noise Measurement).......................................................................... 78 6.1.3 Block Selection for Refinement ........................................................................................... 78 6.2 NON-LOCAL MEANS REFINEMENT................................................................................................... 79 6.3 P ARAMETER SETTING IN NON-LOCAL MEANS..................................................................................... 82 6.4 DECODING WITH THE REFINED SIDE INFORMATION.............................................................................. 83 6.5 EXPERIMENTAL RESULTS................................................................................................................. 84 CHAPTER 7 CONCLUSIONS AND FUTURE WORK .............................................................................. 87 BIBLIOGRAPHY ..................................................................................................................................... 88 PUBLICATION LIST ................................................................................................................................91 | |
| dc.language.iso | en | |
| dc.subject | 附帶消息 | zh_TW |
| dc.subject | 通用圖形處理器 | zh_TW |
| dc.subject | 多核心中央處理器 | zh_TW |
| dc.subject | 分散式視訊壓縮 | zh_TW |
| dc.subject | Wyner-Ziv video coding | en |
| dc.subject | blockmode selection | en |
| dc.subject | GPGPU | en |
| dc.subject | multi-core CPU | en |
| dc.subject | CUDA | en |
| dc.subject | Cloud computing | en |
| dc.subject | parallel computing | en |
| dc.subject | side information refinement | en |
| dc.subject | Distributed video coding | en |
| dc.title | 分散式視訊編碼之旁資訊增強與平行化設計 | zh_TW |
| dc.title | Distributed Video Coding with Improved Side Information
Refinement and Parallelized Architecture Design | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-1 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 李素瑛,歐陽明,杭學鳴,廖弘源,逄愛君 | |
| dc.subject.keyword | 分散式視訊壓縮,附帶消息,通用圖形處理器,多核心中央處理器, | zh_TW |
| dc.subject.keyword | Distributed video coding,Wyner-Ziv video coding,parallel computing,Cloud computing,CUDA,multi-core CPU,GPGPU,blockmode selection,side information refinement, | en |
| dc.relation.page | 92 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-12-28 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊網路與多媒體研究所 | zh_TW |
| 顯示於系所單位： | 資訊網路與多媒體研究所 | |
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