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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62868完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Chun-Wei Chang | en |
| dc.contributor.author | 張鈞維 | zh_TW |
| dc.date.accessioned | 2021-06-16T16:13:03Z | - |
| dc.date.available | 2018-02-21 | |
| dc.date.copyright | 2013-02-21 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-02-08 | |
| dc.identifier.citation | [1] J. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, “Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658–2668, Dec. 2006.
[2] J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification,” IEEE J. Solid State Circuits, vol. 44, no. 4, pp. 1057–1066, Apr. 2009. [3] I. Ahmed, J. Mulder, and D. Johns, “A 50 MS/s 9.9mW Pipelined ADC with 58 dB SNDR in 0.18 um CMOS Using Capacitive Charge-Pumps,” IEEE International. Solid-State Circuits Conf., pp. 164–165, Feb. 2009. [4] I. Ahmed , J. Mulder and D.Johns“A Low-Power Capacitive Charge Pump Based Pipelined ADC” IEEE J. Solid-State Circuits, vol. 45, No. 5, pp. 1016 – 1027, May 2010. [5] Kim, J.K.-R. and B. Murmann, “A 12-b, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration” IEEE J. Solid-State Circuits, Vol 47, No. 7, pp. 2141 – 2151, September 2012 [6] B. Hershberg, et. al. “Ring Amplifiers for Switched-Capacitor Circuits,” IEEE International. Solid-State Circuits Conf., pp. 460 – 462, Feb. 2012. [7] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita and U. Moon, “ A 61.5dB SNDR Pipelined ADC Using Simple Highly-Scalable Ring Amplifiers” IEEE Symposium on VLSI Circuits Digest of Technical Papers, June 2012. [8] Junhua Shen and Peter R. Kinget, “Current-Charge-Pump Residue Amplification for Ultra-Low-Power Pipelined ADCs,” IEEE Trans. Circuits Syst. II, vol. 58, no. 7, pp. 412-416, Jul. 2011. [9] H. Yang and R. Sarpeshkar, “A Time-Based Energy-Efficient Analog-To-Digital Converter,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1590–1601, Aug. 2005. [10] A. Chow and H.-S. Lee, “Offset Cancellation for Zero Crossing Based Circuits,” IEEE International Symposium on Circuits and Systems, pp. 1719 – 1722, 2010. [11] J.-E. Jang, “Comparator-Based Switched-Capacitor Pipelined ADC with Background offset calibration,” IEEE International Symposium on Circuits and Systems, pp. 253 – 256, 2011. [12] S. Lee, A. Chandrakasan, and H.-S. Lee, “A 12b 5-to-50MS/s 0.5-to-1V Voltage Scalable Zero-Crossing Based Pipelined ADC,” IEEE European Solid-State Circuits Conf, pp.355-358, 2011. [13] I. Wang and S. Liu, “An Integrating Analog-to-Digital Data Converter with Variable Resolution” IEEE International Symposium on VLSI Design Automation and Test, 2010. [14] Taehwan Oh, Venkatram, H., Guerber, J. and U.K Moon, “Correlated Jitter Sampling for Jitter Cancellation in Pipelined TDC” IEEE International Symposium on Circuits and Systems, pp. 810 – 813, May 2012. [15] M. Lee and A. A. Abidi, “A 9b 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769–777, Apr. 2008. [16] Y-H Seo, J-S Kim, H-J Park, and J-Y Sim “A 0.63ps Resolution, 11b Pipeline TDC in 0.13μm CMO” IEEE Symposium on VLSI Circuits Digest of Technical Papers. Dig., pp.152-153, Jun. 2011. [17] P. Chen, C.-C. Chen, and Y.-S. Shen, “A Low-Cost Low Power CMOS Time-to-Digital Converter Based on Pulse Stretching,” IEEE Trans. Nucl. Sci., vol. 53, no. 4, pp. 2215–2220, Aug. 2006. [18] S.H. Lewis and H.S. Fetterman, 'A 10-b 20-Msample/s Analog-to-Digital Converter,' IEEE J. Solid-State Circuits, vol.27, no.3, pp.351-358, Mar 1992. [19] O. Stroeble, V. Dias and C. Schwoerer, ”An 80MHz 10b Pipeline ADC with Dynamic Range Doubling and Dynamic Reference Selection” IEEE International Solid-State Circuits Conference, February 2004. [20] B. Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1995. [21] L. Brooks and H.-S. Lee, “A Zero-Crossing-Based 8b 200MS/s Pipelined ADC,” IEEE J. Solid-State Circuits, pp. 460-461, Feb. 2007. [22] A.M. Abo, and P.R. Gray, “A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to- digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May. 1999. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62868 | - |
| dc.description.abstract | 本論文將介紹一個利用時間域後級電壓放大取代傳統轉導放大器放大的管線式類比數位轉換器。隨著先進製程對時脈精確度的提升，利用電流充電電容技巧將電壓訊號線性轉換成時脈訊號。此種技巧的實現只需使用到類比開關、電流源、電容以及閾值偵測比較器就可以達到電壓放大的效果。相較於傳統利用轉導放大器的形式，除了可以省面積外，又可以避免功耗較大的轉導放大器以及類比電壓驅動電路的設計，達到更為省電的目標。
此技巧驗證於65nm CMOS GP製成。根據模擬結果，操作在100MHz之取樣頻率，Nyquist之輸入頻率下，其訊號雜訊失真比為54.74dB，有效位元為8.8位元，總功耗為3.9mW。效能品質( FoM )為88 fJ/C.S，主動電路所佔之面積為0.09mm2。 | zh_TW |
| dc.description.abstract | A pipelined ADC with time-domain MDAC, instead of using OTA topology, is presented. It takes advantage of the improved timing resolution in advanced CMOS technologies by transforming the voltage-domain signal into equivalent timing signal.
This technique simply uses analog switches, current sources, capacitors and threshold-detecting comparators. Compared to conventional OTA-based pipeline ADC, it occupies a small area, and achieves power efficiency by eliminating operational transconductance amplifier and avoiding design of power-hungry buffer for reference voltages. This proof-of-concept prototype is demonstrated in a 65nm CMOS GP. According to Hspice simulation results, this prototype can operate at 100MHz. Signal-to-Noise and Distortion Ratio are 54.74dB when the input frequency is Nyquist rate, and the Effective Number of Bit is 8.8 bit. The total power consumption is 3.9mW. The figure of merit (FoM) is 88 f.J/C.S and its active area only occupies 0.09 mm2 . | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T16:13:03Z (GMT). No. of bitstreams: 1 ntu-102-R99943132-1.pdf: 1495877 bytes, checksum: 9a96968aef913b8ab8f3c8bd61c95cf7 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 摘要 I
Abstract II Contents III List of Figures VII List of Tables XI Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 1 Chapter 2 Fundamentals of ADC 3 2.1 Introduction 3 2.2 Performance Metrics 3 2.2.1 Static Performance 3 2.2.2 Dynamic Performance 5 2.3 ADC Architectures 7 2.3.1 Flash ADC Architecture 7 2.3.2 Successive-approximation ADC Architecture 9 2.3.3 Pipelined ADC Architecture 11 2.3.4 Continuous-time Delta-sigma ADC Architecture 12 2.4 Summary 13 Chapter 3 Proposed Pipelined ADC Using Time-domain MDAC .14 3.1 Introduction 14 3.2 Techiques to Eliminate OPAMPs Design 14 3.2.1 Prior Work 1: Zero-crossing-based Converter 17 3.2.2 Prior Work 2: Dynamic Source Follower Residue Amplification 21 3.2.3 Prior Work 3: Ring amplifier 24 3.2.4 Prior Work 4: Time-based ADC 25 3.2.5 Proposed Time-domian MDAC in pipelined ADC 27 3.3 Design Consideration of Time-domain MDAC 34 3.3.1 Gain Mismatch 34 3.3.2 Nonlinearity of Current Source 35 3.3.3 Finite Comparator Delay Time 41 3.3.4 Noise of Time-domain MDAC 42 3.3.5 Timing Meta-stability 43 3.3.6 Other Limitations 43 3.4 Summary 44 Chapter 4 Proposed Building Blocks and Circuit Implementation .46 4.1 Introduction 46 4.2 Building Blocks and Circuit Implementation 47 4.2.1 MDAC 47 4.2.2 Sub-ADC 57 4.2.3 Clock Generator 62 4.2.4 Bootstrap Circuit 65 4.3 Simulation Results 66 4.3.1 Time-domain MDAC Transient Analysis 66 4.3.2 FFT Simulation 68 4.4 Summary 70 Chapter 5 Measurement Results 71 5.1 Introduction 71 5.2 Floor Plan and Layout 71 5.3 PCB design 74 5.4 Test Setup 77 5.5 Measurement Results 79 5.5.1 Dynamic Performance 80 5.5.2 Static Performance 84 5.6 Summary 89 Chapter 6 Conclusions 90 Bibliography 92 | |
| dc.language.iso | en | |
| dc.subject | 管線式類比數位轉換器 | zh_TW |
| dc.subject | 時間域 | zh_TW |
| dc.subject | Pipelined ADC | en |
| dc.subject | Time-domain | en |
| dc.title | 一個利用時間軸轉換技巧作後級放大的低功率導管式類比數位轉換器 | zh_TW |
| dc.title | A Low Power Pipelined ADC Using Time-Domain MDAC For Residue Amplification | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 盧奕璋,郭建宏 | |
| dc.subject.keyword | 管線式類比數位轉換器,時間域, | zh_TW |
| dc.subject.keyword | Pipelined ADC,Time-domain, | en |
| dc.relation.page | 96 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-02-08 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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