以平行雜序執行方式達成快速且精準之多核心系統晶片虛擬平台模擬方法

Abstract

隨著積體電路的複雜化，晶片開發者開始採用虛擬平台模擬技術進行系統架構探索及軟體開發等任務，採用虛擬平台模擬技術的優勢在於可以利用高階語言快速建構硬體模型，開發者因此能夠有效率地驗證設計之系統原型是否達到預期的功能；除此之外，虛擬平台上建構之系統原型是由軟體構成，設計者可以任意地在系統原型上增添不足之功能（或刪除不當之設計）而不必擔心實體硬體元件的花費問題。由於在系統設計初期，設計者需要不斷確認其架構與功能是否合乎需求，能夠快速建構系統原型且具備低成本特性的虛擬平台模擬技術開始在近年來被廣泛應用於系統晶片開發。 然而，使用虛擬平台模擬技術開發系統層級設計常必須在模擬效能與模擬精確度上進行取捨。一般來說，使用虛擬平台模擬複雜之系統晶片常常需要耗費大量時間，為了提高模擬效能，一般虛擬平台模擬技術是在建置硬體模型時採取較高層級的抽象化以減少模擬硬體時所需要的同步動作而達到較佳的模擬速度，可是，採用高抽象化硬體模型常常無法精確地反映出的硬體行為，例如：不同硬體同時存取記憶體所造成資料傳輸的延遲狀況，所以以抽象化提高模擬速度的方法常因此犧牲掉模擬精確度。由於開發者必須仰賴夠精確的模擬結果才能確認系統原型的架構與規格，所以如何解決虛擬平台模擬技術中模擬效能與模擬精確度無法兩全的狀況是一個非常有挑戰性的課題。 為了克服虛擬平台模擬無法兼顧模擬效能與準確度的問題，我們先仔細地分析虛擬平台模擬硬體的演算法，我們發現虛擬平台模擬速度緩慢的主要原因來自於模擬中大量的同步行為，這種狀況是因為虛擬平台是由軟體所構建，所以模擬器以循序的方式模擬在硬體同時動作的行為，為了能夠精確地模擬出硬體行為，一般的虛擬平台模擬方法常常在模擬中對不同的硬體模擬程序進行同步，這些頻繁的同步行為往往造成模擬上的龐大負擔而使得模擬效能低落，為了解決模擬效能低落的問題，我們提出了一個平行雜序模擬演算法減少模擬中不必要的同步動作，這個模擬演算法中應用了追蹤導向模擬技術，使得模擬硬體中，即使同步行為減少了，我們提出的模擬演算法亦能補償硬體的延遲時間以確保模擬的精確度。當我們使用此方法在以SystemC語法建置的多核心系統虛擬平台上，相較原始SystemC所使用的模擬方法，模擬速度增進比率可達165倍且模擬結果亦達到時脈之精確度。

Virtual platform simulation is an essential technique in early-stage system-level design space exploration and embedded software development. Generally, a design prototype on a virtual platform is constructed by software language. Virtual platform simulation then has the advantages in high flexibility and low cost to help system-level hardware/software designers validate their design. For example, testing and/or application software can be verified on the virtual hardware platform before a hardware implementation is available. Therefore, virtual platform simulation is gradually applied for system-level design development. However, given the increasing complexity of the Multi-Processor Silicon-on-Chip (MPSoC) designs, even the state-of-the-art virtual platform simulation algorithms may still suffer from the simulation speed issue. As for the simulation speed-up, previous work suggests raising the virtual platform simulation to higher abstraction levels, with the tradeoff made in less accurate modeling. However, accurate simulation results are necessary for MPSoC virtual platform simulation applications, such as performance evaluation and architecture exploration. Thus, achieving both high speed and accurate outcome remains a necessity and a big challenge in MPSoC virtual platform simulation. To overcome the above challenge, we first carefully examine the key factor that determines the trade-offs between simulation efficiency and accuracy. Then we find that the factor results from the degree of synchronizations among software-constructed hardware simulation processes (HSPs). For synchronization reduction to break through the trade off, we propose a parallel out-of-order execution approach to efficiently perform simulation scheduling. Our approach can schedule HSPs to out-of-orderly simulate hardware in concurrence and thus reduces a great portion of synchronization for simulation speed-up. Moreover, this approach contains a dynamic trace-driven simulation technique which can on-the-fly reconstruct the simulated time and maintain the accurate cycle information. We implement the above-mentioned algorithms by modifying the SystemC kernel (i.e. the implementation of simulation scheduling). The experimental results show that our proposed MPSoC virtual platform simulation approach can outperform the conventional approach in simulation speed by up to 165X. In addition, with the help of the dynamic trace-driven simulation technique, our MPSoC virtual platform simulation guarantees cycle accuracy.