請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62109完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Pao-Yang Tsai | en |
| dc.contributor.author | 蔡博仰 | zh_TW |
| dc.date.accessioned | 2021-06-16T13:28:15Z | - |
| dc.date.available | 2015-08-23 | |
| dc.date.copyright | 2013-08-23 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-07-22 | |
| dc.identifier.citation | [1] J. Yang, T. L. Naing, R. W. Brodersen, “A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1469-1478, Aug. 2010.
[2] J. Guerber, M. Gande, H. Venkatram, A. Waters, U.-K. Moon, “A 10b Ternary SAR ADC with decision time quantization based redundancy,” in IEEE ASSCC Dig. Tech. Papers, Nov. 2011, pp. 65-68. [3] J.-E. Jang, “Comparator-Based Switched-Capacitor Pipelined ADC with Background offset calibration,” IEEE International Symposium on Circuits and Systems, pp. 253–256, 2011. [4] C.-C Liu, S.-J Chang, G.-Y Huang, Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. [5] K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, G. V. Weide, “A 480mW 2.6GS/s 10b 65nm CMOS Time-interleaved ADC with 48.5dB SNDR up to Nyquist,” in IEEE ISSCC Dig. Tech. Papers, 2011, pp. 180-181. [6] E. Alpman, H. Lakdawala, L. R. Carley, K. Soumyanath “A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 76-77. [7] B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, “Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, Jul. 2004. [8] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, T. R. Viswanathan, “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351-358, Mar. 1992. [9] R. Vitek, E. Gordon, S. Maerkovich, A. Beidas, “A 0.015mm2 63fJ/conversion-step 10-Bit 220MS/s SAR ADC With 1.5b/step Redundancy and Digital Metastability Correction,” Proc. Custom Integrated Circuits Conf., pp. 576-579, Sep. 2012. [10] V. Hariprasath, J. Guerber, S.-H. Lee, U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy efficiency,” Electron. Lett., vol. 46, pp. 620-621, Apr. 2010. [11] W.-Y. Pang, C.-S. Wang, Y.-K. Chang, N.-K. Chou, and C.-K. Wang, “A 10-bit 500-KS/s low power SAR ADC with splitting capacitor for bio-medical applications,” in IEEE ASSCC Dig. Tech. Papers, 2009, pp. 149–152. [12] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, R. P. Martins, F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1111–1121, Jun. 2010. [13] C.-H. Kuo ,C.-E. Hsieh, “A high energy-efficiency SAR ADC based on partial floating capacitor switching technique,” Proc. IEEE ESSCIRC, pp. 475–478, 2011. [14] A. M. Abo, P. R. Gray, “A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May. 1999. [15] H.-Y. Tai, H.-W. Chen ,H.-S. Chen, ”A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS,” in IEEE Symp. VLSI Circuits Dig., Jun. 2012, pp. 92-93. [16] T. Jiang, W. Liu, F. Y. Zhong, C. Zhong, K. Hu, P. Chiang, “A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 2444-2453, Oct. 2012. [17] Y.-S Shu, “A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators,” in IEEE Symp. VLSI Circuits Dig., Jun. 2012, pp. 26-27. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62109 | - |
| dc.description.abstract | 一個以40奈米CMOS製程實現的單通道非同步六位元每秒十二億五千萬次的連續漸近式類比數位轉換器被提出。
此設計採用了延時轉移技術，去幫助比較器跳過亞穩態的時段。它轉移比較器的延遲時間，產生一點五位元的閾值範圍，以加快比較速度，並補償動態偏移。此外，為了最大化一個時鐘周期的使用效率，加入自動取樣電路，以適當地分配取樣相位及轉換相位。 此類比數位轉換器的最高信噪失真比達37.1dB，供應1.2伏特時，功耗為5.3毫瓦，性能係數為73fJ/c.-s。因為不需要額外的校正電路，主電路所占面積只有0.004平方毫米。 | zh_TW |
| dc.description.abstract | A single channel, asynchronous, 6-bit, 1.25GS/s SAR ADC in 40nm CMOS technology is proposed.
In this design, the delay-shift technique is applied, which helps the comparator skip the period of metastability. It shifts the comparator delay, generating the 1.5b threshold range to accelerate the comparison speed and compensate the dynamic offset by the redundancy. Besides, so as to maximize the efficiency of the use of a clock period, The Duty-cycle-auto-adjusting (DCAA) circuit is added to assign the proportion of the sampling phase and the conversion phase properly. This ADC achieves 37.1dB peak SNDR, consumes 5.3mW at 1.2V supply, and results in an FoM of 73fJ/c.-s. Because there is no extra circuit for calibration, the core circuit only occupies an area of 0.004mm^2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T13:28:15Z (GMT). No. of bitstreams: 1 ntu-102-R00943004-1.pdf: 5906216 bytes, checksum: c72592ed570b1d4b2b0dcd57462a0814 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 致謝…………………………………………………………………………………...III
摘要…………………………………………………………………………………..IV Abstract....... V Contents…... VI List of Figures X List of Tables XV Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog to Digital Converter 3 2.1 Introduction 3 2.2 Performance Metrics 3 2.2.1 Offset and Gain Error 3 2.2.2 Differential and Integral Nonlinearity (DNL, and INL) 4 2.2.3 Signal-to-Noise Ratio (SNR) 5 2.2.4 Total Harmonic Distortion (THD) 6 2.2.5 Spurious-Free Dynamic Range (SFDR) 7 2.2.6 Signal-to-Noise and Distortion Ratio (SNDR) 7 2.2.7 Effective Number of Bits (ENOB) 7 2.2.8 Figure of Merit (FoM) 8 2.3 Architecture of Analog to Digital Converters 8 2.3.1 Flash ADC Architecture 9 2.3.2 Two-step ADC Architecture 10 2.3.3 Pipelined ADC Architecture 11 2.3.4 Continuous-time Delta-sigma ADC Architecture 13 2.3.5 Successive-approximation ADC Architecture 14 2.4 Summary 16 Chapter 3 Proposed Delay-shift Technique and Duty-cycle-auto-adjusting 16 3.1 Introduction 17 3.1.1 Analysis of Comparison Time and Metastability 18 3.2 Delay-Shift Technique 21 3.2.1 1.5-bit Stages In Pipelined ADC 21 3.2.2 A 10-Bit 220MS/s SAR ADC with 1.5b/step Redundancy 23 3.2.3 Ternary SAR Architecture 26 3.2.4 Proposed Delay-Shift Technique 30 3.3 Duty-cycle-auto-adjusting 35 3.3.1 Asynchronous Clock Control 35 3.3.2 Clock Generation 38 3.3.3 Proposed Duty-cycle-auto-adjusting Circuit 39 3.4 Summary 41 Chapter 4 Circuit Implementation and Simulation Results 42 4.1 Introduction 42 4.2 Building Blocks and Circuit Implementation 42 4.2.1 Comparator 43 4.2.2 Capacitor Array 46 4.2.2.1 Monotonic Switching Method 46 4.2.2.2 Proposed Switching Method 49 4.2.3 Bootstrap Switches 53 4.2.4 SAR Logic 55 4.3 Overall ADC Simulation Results 62 4.3.1 Algorithm Simulation 62 4.3.2 Transistor Level Simulation 63 4.4 Summary 66 Chapter 5 Measurement Results 67 5.1 Introduction 67 5.2 Measurement Setup 67 5.3 PCB Design 70 5.4 Floor Plan and Layout 74 5.5 Measurement Results 76 5.5.1 Static Performance 78 5.5.2 Dynamic Performance 78 5.6 Summary 81 Chapter 6 Conclusions 83 Bibliography 84 | |
| dc.language.iso | en | |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 類比/數位轉換器 | zh_TW |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | 高速 | zh_TW |
| dc.subject | low power | en |
| dc.subject | analog to digital converter | en |
| dc.subject | SAR | en |
| dc.subject | high speed | en |
| dc.title | 一個零點零零四平方毫米單通道六位元每秒十二億五千萬次取樣的延時轉移連續漸近式類比數位轉換器 | zh_TW |
| dc.title | A 0.004mm^2 Single Channel 6b 1.25GS/s Delay-Shift SAR ADC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),蔡宗亨(Tsung-Heng Tsai) | |
| dc.subject.keyword | 類比/數位轉換器,連續漸進式,高速,低功率, | zh_TW |
| dc.subject.keyword | analog to digital converter,SAR,high speed,low power, | en |
| dc.relation.page | 86 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-07-23 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-102-1.pdf 未授權公開取用 | 5.77 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。