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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電信工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/61980
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor吳瑞北
dc.contributor.authorYi-Chen Wuen
dc.contributor.author吳宜真zh_TW
dc.date.accessioned2021-06-16T13:21:34Z-
dc.date.available2013-08-06
dc.date.copyright2013-08-06
dc.date.issued2013
dc.date.submitted2013-07-25
dc.identifier.citation[1] W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, “Demystifying 3D ICs: The pros and cons of going vertical,” IEEE Design Test Computers, vol. 22, no. 6, pp. 498–510, Nov. 2005.
[2] J. S. Pak, C. Ryu, and J. Kim, “Electrical characterization of through silicon via (TSV) depending on structural and material parameters Based on 3D full wave simulation,” in Int’l. Conf. Electron. Mat. Packag., Yuseong-gu, Daejeon, Korea, Nov. 11–19, 2007.
[3] N. Kim, D. Wu, D. Kim, A. Rahman, and P. Wu, “Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV),” in IEEE Electron. Compon. Technol. Conf., Lake Buena Vista, Florida, USA, May 31–June 3, 2011, pp.1160–1167.
[4] H. Kim, J. Cho, M. Kim, K. Kim, J. Lee, H. Lee, K. Park, K. Choi, H.-C. Bae, J. Kim, and J. Kim, “Measurement and analysis of a high-speed TSV channel,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 2, no. 10, pp.1672–1685, Oct. 2012.
[5] J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M.-S. Suh, K.-Y. Byun, and J. Kim, “High-frequency scalable electrical model and analysis of a through silicon via (TSV),” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 2, pp.181–195, Feb. 2011.
[6] T. G. Lim, Y. M. Khoo, C. S. Selvanayagam, D. S. W. Ho, R. Li, X. Zhang, G. Shan, and X. Y. Zhong, “Through silicon via interposer for millimetre wave applications,” in IEEE Electron. Compon. Technol. Conf., Lake Buena Vista, Florida, USA, May 31–June 3, 2011, pp.577–582.
[7] C.-H. Lin, C. Liu, H.-K. Huang, K.C. Fan, and H.-H. Lee, “Electrical model analysis of RF/high-speed performance for different designed TSV patterns by wideband double side measurement techniques,” in Int’l. Microsyst., Packag., Assemb. Circuits Technol. Conf., Taipei, Taiwan, ROC, Oct. 24–26, 2012, pp.72–75.
[8] K.-C. Lu, T.-S. Horng, H.-H. Li, K.-C. Fan, T.-Y. Huang, and C.-H. Lin, “Scalable modeling and wideband measurement techniques for a signal TSV surrounded by multiple ground TSVs for RF/high-speed applications,” in IEEE Electron. Compon. Technol. Conf., San Diego, California, USA, May 29–June 3, 2012, pp. 1023–1026.
[9] E. Eid, T. Lacrevaz, G. Houzet, C. Bermond, B. Flechet, A. Farcy, F. Calmon, and P. Leduc, “Effects of silicon substrate coupling phenomena on signal integrity for RF or high speed communications in 3DIC,” in IEEE Electron. Compon. Technol. Conf., San Diego, California, USA, May 29–June 3, 2012, pp. 827–833.
[10] J. Kim, D. Jung, J. Cho, J. S. Pak, J. M. Yook, J. C. Kim, and J. Kim, “High-frequency measurements of TSV failures,” in IEEE Electron. Compon. Technol. Conf., San Diego, California, USA, May 29–June 3, 2012, pp. 298–303.
[11] D. H. Jung, J. Kim, H. Kim, J. J. Kim, J. Kim, J. S. Pak, J.-M. Yook, and J. C. Kim, “Frequency and time domain measurement of through-silicon via (TSV) failure,” in IEEE Electrical Performance Electron. Packag. Syst., Tempe, Arizona, USA, Oct. 21–24, 2012, pp. 331–334.
[12] K. J. Han, M. Swaminathan, and T. Bandyopadhyay, “Electromagnetic modeling of through-silicon via (TSV) interconnections using cylindrical modal basis functions,” IEEE Trans. Adv. Packag., vol. 33, no. 4, pp. 804–817, Nov. 2010.
[13] C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, “High frequency electrical model of through wafer via for 3-D stacked chip packaging,” in IEEE Electron. Systeminteg. Technol. Conf., Dresden, Germany, Sept. 5–7, 2006, pp. 215–220.
[14] D. H. Kim, S. Mukhopadhyay, and S. K. Lim, “Fast and accurate analytical modeling of through-silicon-via capacitive coupling,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 2, pp.168–180, Feb. 2011.
[15] J. Kim, E. Song, J. Cho, J. S. Pak, J. Lee, H. Lee, K. Park, and J. Kim, “Through silicon via (TSV) equalizer,” in IEEE Electrical Performance Electron. Packag. Syst., Tigard, Oregon, USA, Oct. 19–21, 2009, pp.13–16.
[16] L. Liang, M. Miao, Z. Li, S. Xu, Y. Zhang, and X. Zhang, “3D modeling and electrical characteristics of through-silicon-via (TSV) in 3D integrated circuits,” in IEEE Int’l. Conf. Electron. Packag. Technol. High Density Packag., Shanghai, China, Aug. 8–11, 2011.
[17] L. Zhang, W. Yu, Y. Zhang, R. Wang, A. Deutsch, G. A. Katopis, D. M. Dreps, J. Buckwalter, E. S. Kuh, and C.-K. Cheng, “Analysis and optimization of low-power passive equalizers for CPU–memory links,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 9, pp. 1406–1420, Sep. 2011.
[18] R. Sun, J. Park, F. O’Mahony, and C. P. Yue, “A low-power, 20-Gb/s continuous-time adaptive passive equalizer,” in IEEE Int’l. Symp. Circuits Syst., Kobe, Japan, May 23–26, 2005, vol. 2, pp. 920–923.
[19] J. Shin and K. Aygun, “On-package continuous-time equalizer using embedded passive components,” in IEEE Electrical Performance Electron. Packag., Atlanta, Georgia, USA, Oct. 29–31, 2007, pp. 147–150.
[20] R.-B. Sun, C.-Y. Wen, and R.-B. Wu, “Passive equalizer design for through silicon vias with perfect compensation,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 11, pp. 1815–1822, Nov. 2011.
[21] Q2D Extractor, Version 8.0, Ansys, Inc. [Online]. Available: www.ansys.com
[22] C. R. Paul, Analysis of Multiconductor Transmission Lines. New York: Wiley, 1994, chs. 7.
[23] HFSS (High Frequency Structure Simulator), Version 11.0, Ansys, Inc. [Online]. Available: www.ansys.com
[24] S. Mondal, S.-J. Shih, F.-H. Chen, and T.-M. Pan, “Structural and electrical characteristics of Lu2O3 dielectric embedded MIM capacitors for analog IC applications,” IEEE Trans. Electron Devices, vol. 59, no. 6, pp. 1750–1756, June 2012.
[25] K.-W. Kwon, C.-S. Kang, S.-O. Park, H.-K. Kang, and S.-T. Ahn, “Thermally robust Ta2O5 capacitor for the 256-Mbit DRAM” IEEE Trans. Electron Devices, vol. 43, no. 6, pp. 919–923, Aug. 2002.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/61980-
dc.description.abstract隨著電子用品尺寸縮小,如何在有限空間中極大化積體電路的功能成為相當重要的議題。三維積體電路透過垂直堆疊結構將多功能晶片整合於較小的體積中,為目前最具可行性的方案。垂直堆疊結構裡最常使用的技術為鎊線與微凸塊,但由於直通矽晶連通柱具有較短傳輸路徑、較高輸入輸出密度與較低製造成本的優勢,因此逐漸受到重視。然而,萃取垂直堆疊多層直通矽晶連通柱的傳輸特性不僅代價高昂,實作可行性也低。此外,多層直通矽晶連通柱的損耗特性會造成訊號失真,降低訊號完整度。根據上述兩點,本篇論文提出兩組鍊狀型結構進行多層直通矽晶連通柱傳輸特性萃取,並設計一組電阻電容型等化器以改善訊號失真的問題。
在傳輸特性萃取的部份,本篇論文提出兩組鍊狀型結構,透過將直通矽晶連通柱水平連結,達到模擬垂直堆疊的直通矽晶連通柱的目標。此外,亦針對兩組鍊狀型結構分別設計相對應的校準方式,以除去傳輸線效應與訊號直通矽晶連通柱間的耦合效應。研究成果將有助於以低成本且高可行性的方式萃取垂直堆疊的直通矽晶連通柱傳輸特性。
在損耗補償的部份,本篇論文根據簡化的直通矽晶連通柱等效電路設計一組電阻電容型等化器,具有低功耗、高頻寬與適用於廣泛製程的優勢。此外,以十層垂直堆疊的直通矽晶連通柱結構為案例,分析本篇論文所提出的電阻電容型等化器效能,並檢視實際製作的可能性。透過採行此電阻電容型等化器,可大幅降低訊號失真的問題,提昇訊號傳輸品質與系統整體效能。
zh_TW
dc.description.abstractOptimizing the performance of integrated circuits (IC) in a limited space has become an important issue as electronic devices continue to decrease in size. One of the most promising technologies that aim to solve this issue is called three dimensional integrated circuits (3D-IC), which stacks ICs vertically. Compared to traditional techniques such as wire-bonding and microbumps, through-silicon-via (TSV) provides shorter transmission paths, higher input/output (I/O) density and lower cost. However, characterization of stacked TSVs is difficult and expensive. Furthermore, lossy TSVs may damage the signal integrity of systems. Therefore, this thesis proposes a solution consisting of two structures and an equalizer to solve the problems mentioned above.
In order to extract the transmission effect of a single TSV, two sets of horizontally connected TSVs are designed. Under weak coupling conditions, the effect caused by transmission lines and coupling among signals can be eliminated through a calibration mechanism. Hence, extraction results can be used to predict the behavior of stacked TSVs. In addition, the characterization of TSVs is much more feasible and can reduce costs by using the methods.
The design formulas of RC equalizers can be derived from the simplified equivalent circuit model of TSVs. Since mutual capacitance between TSVs has been taken into consideration, this RC equalizer can be applied to most processes operating in high frequencies. In addition, RC equalizers have lower power consumption and can provide wideband compensation. At the end, a structure of ten stacked TSVs is taken as an example to demonstrate the performance of RC equalizers and to evaluate the feasibility as well. The result shows that implementing RC equalizers can significantly improve the
quality of signals.
en
dc.description.provenanceMade available in DSpace on 2021-06-16T13:21:34Z (GMT). No. of bitstreams: 1
ntu-102-R00942018-1.pdf: 2721370 bytes, checksum: 9fc2eb6c6c777b50b7791fe151529677 (MD5)
Previous issue date: 2013
en
dc.description.tableofcontents誌謝 I
摘要 II
Abstract III
內容 V
圖目錄 VII
表目錄 XI
第一章、 緒論 1
1-1. 研究動機 1
1-2. 文獻回顧 2
1-3. 研究貢獻 5
1-4. 章節概要 6
第二章、 三維積體電路直通矽晶連通柱與等化器原理 7
2-1. 鍊狀式結構中直通矽晶連通柱間的弱耦合效應 7
2-2. 直通矽晶連通柱間耦合效應之等效傳輸矩陣 12
2-3. 直通矽晶連通柱的等效電路模型 19
2-4. 等化器原理 21
2-5. 電阻電容型等化器的設計原理 24
第三章、 直通矽晶連通柱之特性萃取 28
3-1. 傳輸特性萃取結構設計之二層金屬結構 28
3-2. 傳輸特性萃取結構設計之三層金屬結構 33
3-3. 製程參數 37
3-4. 模擬結果與討論 38
3-5. 實際應用討論 49
第四章、 直通矽晶連通柱之損耗補償 52
4-1. 直通矽晶連通柱之重要性分析與其簡化等效電路模型 52
4-2. 等化器設計方式 58
4-3. 模擬結果與討論 61
4-4. 實際應用之可行性評估 66
第五章、 結論與未來展望 69
5-1. 結論 69
5-2. 未來展望 70
參考文獻 71
dc.language.isozh-TW
dc.subject直通矽晶連通柱zh_TW
dc.subject耦合效應zh_TW
dc.subject特性萃取zh_TW
dc.subject等效傳輸矩陣zh_TW
dc.subjectcharacterizationen
dc.subjectcalibrationen
dc.subjectcouplingen
dc.subjectequivalent transmission matrixen
dc.title三維積體電路之直通矽晶連通柱的傳輸特性萃取與損耗補償zh_TW
dc.titleExtraction and Compensation of Through Silicon Vias in 3D-ICen
dc.typeThesis
dc.date.schoolyear101-2
dc.description.degree碩士
dc.contributor.oralexamcommittee楊明宗,吳宗霖,洪子聖,林建民
dc.subject.keyword特性萃取,直通矽晶連通柱,耦合效應,等效傳輸矩陣,zh_TW
dc.subject.keywordcharacterization,calibration,coupling,equivalent transmission matrix,en
dc.relation.page84
dc.rights.note有償授權
dc.date.accepted2013-07-25
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電信工程學研究所zh_TW
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