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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃天偉 | |
dc.contributor.author | Chia-Lin Hsieh | en |
dc.contributor.author | 謝佳霖 | zh_TW |
dc.date.accessioned | 2021-06-16T13:20:26Z | - |
dc.date.available | 2015-07-30 | |
dc.date.copyright | 2013-07-30 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-07-25 | |
dc.identifier.citation | [1] E. Cohen, S. Ravid, and D. Ritter, “An ultra low power LNA with 15dB gain and 4.4dB NF in 90nm CMOS process for 60 GHz phase array radio,” in IEEE Radio Frequency Integrated Circuits Symposium Digest, June 2008, pp. 61–64.
[2] W.-H. Lin, J.-H. Tsai, Y.-N. Jen, T.-W. Huang, and H. Wang, “A 0.7-V 60-GHz low-power LNA with forward body bias technique in 90 nm CMOS process,” in 2009 European Microwave Integrated Circuits Conference Digest, pp. 393-396, Rome, Italy, September 2009. [3] B.-J. Huang, K.-Y. Lin, and H. Wang, “Millimeter-wave low power and miniature CMOS multi-cascode low noise amplifiers with noise reduction topology,” IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 12, pp. 3049-3059, December 2009. [4] H.-C. Yeh, H. Wang, “A Miniature Q-band CMOS LNA with Quadruple-Cascode Topology,” in IEEE MTT-S International Microwave Symposium Digest, June 2011. [5] J.-H. Tsai, W.-C. Chen, T.-P. Wang, T.-W. Huang, and H. Wang, “A miniature Q-band low noise amplifier using 0.13-μm CMOS technology.” IEEE Microwave and Wireless Components Letters, vol. 16, no. 6, pp. 327–329, June 2006. [6] M. Varonnen, M. Karkkainen, M. Kantanen, and K. A. I. Halonen, “Millimeter-wave integrated circuits in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 1991–2002, September 2008. [7] K. Nishikawa, T. Enoki, S. Sugitani, and I. Toyoda, “0.4 V, 5.6 mW InP HEMT V-band Low-Noise Amplifier MMIC,” in IEEE MTT-S International Microwave Symposium Digest, June 2006, pp. 810–813. [8] X. Li, S. Shekhar and D. J. Allstot, “Gm-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2609-2619, December 2005. [9] D. Wu, R. Huang, W. Wong, and Y. Wang, “A 0.4-V low noise amplifier using forward body bias technology for 5 GHz application,” IEEE Microwave and Wireless Components Letters vol. 17, no. 7, pp. 543-545, July 2007. [10] H.-H. Hsieh and L.-H. Lu, “Design of ultra-low-voltage RF frontends with complementary current-reused architectures,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 7, pp. 1445-1458, July 2007. [11] P. Andreani, and H. Sjoland , “Noise Optimization of an Inductively Degenerated CMOS Low Noise Amplifier,” IEEE Transactions on Circuits and Systems- II: Analog and Digital Signal Processing, vol. 48, pp. 835–841, September 2001. [12] J. J. Zhou, and D. J. Allstot, “Monolithic Transformers and Their Application in a Differential CMOS RF Low-Noise Amplifier,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 2020–2027, December 1998. [13] J. R. Long, “Monolithic Transformers for Silicon RF IC Design,” IEEE Journal of Solid-State Circuits, vol. 35, no. 9, pp. 1368–1382, September 2000. [14] W. Chan “A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply” IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 554–564, September 2010. [15] E. Cohen, et al. “Robust 60 GHz 90nm and 40nm CMOS Wideband neutralized Amplifiers with 23dB gain 4.6dB NF and 24% PAE,” Silicon Monolithic Integrated Circuits in RF Systems, pp. 207–210, January 2012. [16] E. Cohen. O. Degani., and D. Ritter “A Wideband Gain-Boosting 8mW LNA with 23dB gain and 4dB NF in 65nm CMOS process for 60 GHz applications,” in IEEE Radio Frequency Integrated Circuits Symposium Digest, pp. 207 – 210, June 2012. [17] H. T. Chou, Z.L. Ke, H.-K. Chiou “A Low Power Compact Size Forward Body-Biased K-Band CMOS Low Noise Amplifier,” Proceedings of the Asia-Pacific Microwave Conference 2011. [18] C. C. Kuo, H. Wang “A 24-GHz Low Power Low Noise Amplifier Using Current Reuse and Body Forward Bias Techniques in 0.18-μm CMOS Technology,” Proceedings of the Asia-Pacific Microwave Conference 2010. [19] J. H. Lee, C. C. Chen and Y. S. Lin “3.7 mW 24 GHz LNA with 10.1 dB gain and 4.5 dB NF in 0.18 μm CMOS technology,” Electronics Letters, vol. 46, no. 19, pp. 1310–1312, September 2010. [20] P. Y. Deng, Y. T. Lo, and J. F. Kiang, “Design of Low-Power K-band Low-Noise Amplifier in 0.18 μm CMOS, “ Applications of Electromagnetism and Student Innovation Competition Awards, pp. 84-88, August 2010. [21] Y. L. Wei, Shawn S. H. Hsu, and J. D. Jin, “A Low-power low-noise amplifier for K-Band applications, ” IEEE Microwave and Wireless Components Letters, vol. 19, no. 2, pp. 116-118, Feb. 2009. [22] A. Sayag, S. Levin, D. Regev, D. Zfira, S. Shapira, D. Goren and D. Ritter, “ A 25 GHz 3.3 dB NF Low Noise Amplifier based upon Slow Wave Transmission Lines and the 0.18 μm CMOS Technology,“ in IEEE Radio Frequency Integrated Circuits Symposium Digest, pp. 373 – 376, June 2008. [23] P. Y. Chang, S. H. Su, S. S. H. Hsu, W. H. Cho, and J.D. Jin “An Ultra-Low-Power Transformer-Feedback 60 GHz Low-Noise Amplifier in 90 nm CMOS ,” IEEE Microwave and Wireless Components Letters, vol. 22, no. 4, pp. 197-199, Feb. 2012. [24] R. P. Jindal, “Compact noise models for MOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2051–2061, Sep. 2006. [25] T. Chang and J. Lin, “1-11 GHz Ultra-Wideband Resistive Ring Mixer in 0.18-μm CMOS Technology,” in IEEE Radio Frequency Integrated Circuits Symposium Digest, June 2006. [26] H. J. Wei, C. Meng, K. C. Tsung and G.-W. Huang, “12~18 GHz Resistive Mixer with a Miniature Marchand Balun using Standard CMOS Process,” Proceedings of the Asia-Pacific Microwave Conference 2009. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/61956 | - |
dc.description.abstract | 本篇論文,為克服互補式金氧半導體製程限制,提出了一系列與低雜訊放大器相關的低功率消耗電路架構之設計與分析。
在第二章中,一個5 GHz、低直流功率消耗之低雜訊放大器被提出且適用於行動通訊應用上。藉由使用電流重複利用、以及基極偏壓等技術,使得此低雜訊放大器於5 GHz能操作在低電源電壓之下且其直流功率消耗只有336微瓦,還能具有相當的小訊號增益。為了進一步地降低雜訊指數與偏壓電流,使用變壓器回授技術有利於在雜訊指數與輸入端匹配的取捨。 在第三章中,一個24 GHz低直流功率消耗之低雜訊放大器被提出。第一級放大器承襲第二章所用增益提升架構,藉由在共閘極放大器的閘極和源極間使用變壓器回授技術,使小訊號增益有效提升和具有很低的雜訊指數。為了在頻率較高的操作下,後級放大器還能有高效率的增益表現,第二級採用共源極放大器搭配變壓器和電容所產生正回授的架構。比起一般的共源極放大器有更高的增益,此方法能在不額外消耗功率的狀況下提供高的增益,使的在低電源電壓之下,其直流功率消耗只有1.5毫瓦。由於兩級電路皆由變壓器所組成,故面積也相當的小。 在第四章中,一個24 GHz低直流功率消耗之低雜訊放大器搭配電阻式的混頻器被提出。承襲第三章所用源極放大器搭配變壓器和電容的正回授架構,為了結合低雜訊放大器和混頻器,頻寬不能太窄,所以第一級放大器採用共源極放大器的閘極和源極間使用變壓器回授技術,比起共閘極的變壓器回授技術能有較寬的頻寬。由於一般在超低功率消耗的操作下,雜訊指數都得靠前級的增益來抑制,故把所有的功耗都使用在低雜訊放大器上,混頻器則使用電阻式的架構,其直流功耗為零。在超低電源電壓之下,整體接收電路直流功率消耗只有683微瓦。由於全部電路都由變壓器所組成,故面積也相當的小。 論文的第一章和第五章則分別是論文的動機介紹和本碩士論文完成的工作之結論。 | zh_TW |
dc.description.abstract | To alleviate the limitations imposed on CMOS technique, some low power techniques are developed for CMOS LNA circuits in this thesis.
In chapter 2, an ultra-low-power and low-noise amplifier is presented for CMOS RF frontends. By employing current-reused, and forward-body-bias techniques, a low-noise amplifier can operate at a reduced supply voltage with micro-watt dc power consumption while maintaining reasonable gain performance at 5 GHz. To reduce noise factor and bias current simultaneously, transformer feedback technique is selected to make compromise between noise figure and input matching. In chapter 3, a low-power 24-GHz transformer LNA is proposed. Similar to chapter 2, a source-gate transformer-coupled common-gate device is utilized in first stage for high gain performance. Furthermore, transformer-based positive-feedback technique is used in second stage to enhance small-signal gain. By employing these two transformer-feedback techniques and forward-body-bias, a low-noise amplifier can operate at a reduced supply voltage with mili-watt dc power consumption while maintaining reasonable gain performance at 24 GHz. In Chapter 4, an ultra-low-power 24-GHz receiver front-end is reported. Different from chapter 3, a gate-source transformer-feedback common-source device is utilized in first stage for wideband matching. Furthermore, transformer-based positive-feedback technique is used in second stage to boost small-signal gain. By employing transformer-feedback technique and forward-body-bias, the LNA can operate at an ultra-low voltage of 0.33V with only 683 μW dc power consumption. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T13:20:26Z (GMT). No. of bitstreams: 1 ntu-102-R00942021-1.pdf: 4658291 bytes, checksum: f3ff2bde8074968f1ee30c913509f747 (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 論文大綱 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES xv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 A 0.6-V 336-μW 5-GHz LNA Using a Low-Voltage and Gain-Enhancement Architecture 3 2.1 Low Power Techniques 3 2.1.1 Reduced Supply Voltage Operation 5 2.1.2 Gm-boosted Common-Gate Topology 6 2.1.3 Forward-Body-Bias Technique 11 2.1.4 Current-Reused Technique 12 2.2 Proposed Circuit Topology 14 2.3 Design of LNA 15 2.3.1 Size and Gate Bias 15 2.3.2 Transformer-Coupled CG 18 2.3.3 DC and AC Analysis 20 2.4 Circuit Implementation 22 2.5 Experimental results 23 2.6 Summary 27 Chapter 3 A 0.6-V 1.56 mW Transformer-Feedback 24-GHz LNA 28 3.1 Transformer-Based Gain-Boosting Techniques 29 3.2 Proposed Circuit Topology 32 3.3 Design of LNA 34 3.3.1 Size and Bias Selectio 34 3.3.2 First Stage-Transformer-Coupled CG 40 3.3.1 Second Stage-Positive-Feedback CS 45 3.3.2 Inter-Stage Transformer Matching 49 3.3.3 Output matching 53 3.3.4 Stability issue 54 3.4 Design flow 56 3.5 Circuit Implementation 57 3.6 Experimental results 58 3.7 Summary 61 Chapter 4 A 0.33-V 683-μW 24-GHz Transformer-Based Micro-Watt Radio 62 4.1 Gate-Source Transformer-Coupled CS 63 4.2 Proposed Circuit Topology 65 4.3 Design of LNA 66 4.3.1 Size and Bias Selection 66 4.3.2 First Stage-Transformer-Coupled CS 69 4.3.3 Second Stage-Positive-Feedback CS 72 4.3.4 Inter-Stage Transformer Matching 75 4.4 Fundamental of Mixer 77 4.5 Design of Mixer 79 4.5.1 Core of resistive ring mixer [25]-[26] 79 4.5.2 Size and Bias Selection 80 4.5.3 RF balun of passive ring mixer 84 4.5.4 LO balun of passive ring mixer 87 4.6 Post-Simulation and Design Flow 90 4.7 Circuit implementation 91 4.8 Experimental results 92 4.9 Summary 98 Chapter 5 Conclusions 99 REFERENCE 101 PUBLICATIONS 105 | |
dc.language.iso | en | |
dc.title | 超低功率消耗之低雜訊放大器和接收器設計與分析 | zh_TW |
dc.title | Design and Analysis of Ultra Low Power LNA and Microwatt Radio | en |
dc.type | Thesis | |
dc.date.schoolyear | 101-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 蔡政翰,張嘉展 | |
dc.subject.keyword | 低雜訊放大器,混頻器, | zh_TW |
dc.subject.keyword | Low-noise amplifier(LNA),resistive ring mixer, | en |
dc.relation.page | 116 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2013-07-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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