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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/61326完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 廖洺漢(Ming-Han Liao) | |
| dc.contributor.author | Li-Cheng Chang | en |
| dc.contributor.author | 張立成 | zh_TW |
| dc.date.accessioned | 2021-06-16T13:01:06Z | - |
| dc.date.available | 2018-08-28 | |
| dc.date.copyright | 2013-08-28 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-08-07 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/61326 | - |
| dc.description.abstract | 本篇論文著重在砷化銦鎵量子井金氧半場效電晶體的製作以及其電性效能的提升，尤其是特別著重在源/汲極阻值的降低，而其內容主要可分為兩大部分，第一部分為利用抬昇式源/汲極來降低阻值；第二部分則是利用超薄介電層之嵌入來降低接觸電阻。
隨著矽基元件逐漸面臨了其發展的瓶頸，三五族化合物半導體因此被視為是下一個世代N型電晶體通道的替代材料。其原因主要是因為三五族化合物擁有較高的電子遷移率以及較低的等效電子質量。然而不像矽基元件成熟的發展，三五族半導體的發展仍有許多困難需要克服，其中一項就是源/汲極阻值的降低。 首先我們製作了1微米閘極長度之砷化銦鎵量子井金氧半場效電晶體，此製程特點包含了非離子佈植的源/汲極、高源/汲極摻雜濃度、低製程熱預算，因此非常適合未來10奈米節點以下的製程。利用改變最上層重摻雜砷化銦鎵層的厚度，我們可以找出最佳化的抬昇式源/汲極結構。我們發現當重摻雜砷化銦鎵層的厚度為30奈米時，元件有最高的飽和電流(0.246 mA/μm)、最高的轉移電導(0.35 mS/μm)及最低的源/汲極阻值(230 Ω-μm)。另外，也因為製程熱預算低的關係，元件的次臨界擺幅(95 mV/dec)與汲極引致能障下降(45 mV/V)也都相當低。 為了繼續降低源/汲極的阻值，源/汲極的接觸電阻必須要再降低。在此，我們將一層超薄介電層嵌入至電晶體源/汲極的金屬與半導體間，形成金屬─絕緣層─半導體的結構。此結構可有效降低原本位於金屬─半導體間，其介面所發生的費米能階釘札，而此費米能階釘札會造成介面間的蕭特基能障居高不下，進而導致接觸電阻的上升。首先我們利用不同接觸金屬(鎳、鋁、鈦)以及不同介電層(氧化鋁、二氧化鈦、氧化鋅)製作出的二極體以及相關的量測圖形來量測其最佳化的結果。由實驗可知當接觸金屬為鋁，介電層為0.6奈米的氧化鋅時，其接觸結構有最低的接觸電阻率(6.7 x 10-9 Ω-cm2)以及相當低的蕭特基能障(0.05 eV)。我們將此結果實際應用在砷化銦鎵量子井金氧半場效電晶體的源/汲極上。在這裡，元件的源/汲極結構是參考前述最佳化抬昇式源/汲極的結果。由1微米閘極長度的元件電性可看出，隨著0.6奈米的氧化鋅嵌入，元件可達到更高的飽和電流(0.416 mA/μm)及轉移電導(0.612 mS/μm)。我們把推測此結果是因為源/汲極的電阻從原本的230 Ω-μm降到了190 Ω-μm。值得注意的是，元件的次臨界擺幅(97 mV/dec)與汲極引致能障下降(53 mV/V)並未因為氧化鋅的嵌入而有明顯的下降。 最後我們將此實驗結果與其他研究團隊的成果做比較，經比較可發現在相近閘極長度的範圍內，我們元件有較好的效能。而我們也預期，隨著元件閘極長度的縮減，元件的效能可以再更進一步的提升。 | zh_TW |
| dc.description.abstract | In this thesis, we focus on the investigation and demonstration of the indium gallium arsenide (In0.53Ga0.47As) quantum-well metal-oxide-semiconductor field-effect transistors (QW-MOSFETs); especially on the source/drain (S/D) regime. Source/drain resistance (RSD) becomes dominant which is mainly attributed to the size scaling and mobility enhancement. To reduce RSD, the strategies for S/D engineering are mainly divided into two parts – raised S/D and metal-insulator-semiconductor (M-I-S) contact.
In the first part, we demonstrate the 1-μm-gate-length (Lg) implant-free In0.53Ga0.47As QW-MOSFETs with raised S/D structure.Through varying the thickness of n++ InGaAs cap layer (Tcap), the optimized structure can be obtained. The optimized Tcap is 30 nm with the highest saturation current (ID,sat) of 0.246 mA/μm and peak transconductance (Gm) of 0.35 mS/μm. We attribute this exceptional on-state performance to the low RSD of 230 Ω-μm at Tcap = 30 nm. On the other hand, due to implant-free gate-last process with low thermal budget, the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) is 95 mV/dec and 45 mV/V, respectively. In order to further reduce the RSD, a novel contact structure, M-I-S contact, is implemented to reduce contact resistance. For conventional metal-semiconductor junction, a strong Fermi-level pinning occurred at the interface and because of the Fermi-level pinning, Schottky barrier (ΦBn) becomes uncontrollable by the metal workfunction and thus results in high ΦBn in general cases. The M-I-S contact with ultra-thin dielectric insertion is used to depin the Fermi-level and thus results in low ΦBn. With inserted dielectric, a tradeoff exists between a decreased Schottky resistance and an increased tunneling resistance. The optimized M-I-S contact structure is obtained to be Al/0.6-nm-ZnO/n++ In0.53Ga0.47As with low ΦBn of 0.05 eV and specific contact resistivity of 6.7 x 10-9 Ω-cm2. ZnO is the optimal choice in this experiment due to the lowest conduction offset with In0.53Ga0.47As. The pinning factor is also obtained and is improved from 0.06 to 0.3 through 0.6-nm-ZnO insertion. Next, we apply this technology on the 1-μm-Lg implant-free In0.53Ga0.47As QW-MOSFETs with optimized raised S/D. ID,sat and peak Gm is 0.416 mA/μm and 0.612 mS/μm, respectively. The RSD is found to be 190 Ω-μm with 70 Ω-μm reduction compared with directly contact. This reduction is attributed to the Rc decreasing through the M-I-S implementation. In addition, off-state characteristics such as SS (97 mV/dec) and DIBL (53 mV/V) is still kept at similar level. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T13:01:06Z (GMT). No. of bitstreams: 1 ntu-102-R00522631-1.pdf: 6062570 bytes, checksum: ae6723a4f3eb8deddf11aa02590cc330 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 口試委員審定書 I
致謝 II 摘要 III Abstract V Table of Contents VII List of Figures X List of Tables XVII Chapter 1. Introduction 1 1.1. On the Scaling Limit of Planar Silicon MOSFETs 1 1.2. The Rationale for Using III-V Compounds 3 1.3. Development of III-V CMOS 7 1.4. Thesis Organization 10 Chapter 2. Fundamentals of MOSFET and Literature Review 13 2.1. Fundamental Operation of MOSFET 13 2.2. Metal-Semiconductor Contact System 22 2.2.1. Schottky Barrier Height 22 2.2.2. Contact Resistance 30 2.3. Novel Structure for Advanced CMOS Technology to Boost On- and Off-state Performance 33 2.3.1. Non Planar and Non Bulk Structure for the Future Applications 33 2.3.2. Strategies for the Source/Drain Resistance Reduction 35 2.3.3. Scaling of Contact Resistance 38 2.4. Literature Review: QW-FETs for the High-Speed and Low-Power Applications 40 Chapter 3. Investigation of Raised S/D Structure on In0.53Ga0.47As QW-MOSFETs 46 3.1. Introduction 46 3.2. Device Fabrication and Characterization 47 3.2.1. Wafer Structure and Characteristics 47 3.2.2. Fabrication Process and Recipe Investigation 50 3.3. Results and Discussions 57 3.4. Conclusions 63 Chapter 4. Demonstration of Fermi-level Depinning for the Ultra-low RSD in In0.53Ga0.47As QW-MOSFETs 65 4.1. Introduction 65 4.2. M-I-S Contact for the Fermi-level Depinning 66 4.2.1. Fermi-level Pinning in M-S Contact 66 4.2.2. The Mechanism of Fermi-level Depinning in M-I-S Contact 69 4.3. Device Fabrication and Characterization 78 4.3.1. Module Study for the Schottky Barrier Height and Contact Resistivity Measurement 78 4.3.2. Fabrication of InGaAs QW-MOSFETs 80 4.4. Results and Discussions 81 4.5. Conclusions 94 Chapter 5. Summaries and Future Works 96 5.1. Summaries 96 5.2. Future Works 98 References 101 | |
| dc.language.iso | zh-TW | |
| dc.subject | 砷化銦鎵 | zh_TW |
| dc.subject | 蕭特基能障 | zh_TW |
| dc.subject | 源/汲極阻值 | zh_TW |
| dc.subject | 費米能階釘札 | zh_TW |
| dc.subject | 量子井金氧半場效電晶體 | zh_TW |
| dc.subject | 接觸電阻率 | zh_TW |
| dc.subject | 抬昇式源/汲極 | zh_TW |
| dc.subject | Schottky barrier | en |
| dc.subject | quantum-well metal-oxide-semiconductor field-effect transistors (QW-MOSFETs) | en |
| dc.subject | source/drain resistance | en |
| dc.subject | raised source/drain | en |
| dc.subject | Fermi-level pinning | en |
| dc.subject | Indium gallium arsenide (In0.53Ga0.47As) | en |
| dc.title | 砷化銦鎵量子井金氧半場效電晶體－利用抬昇式源/汲極結構和超薄介電層之嵌入達到源/汲極阻值的降低 | zh_TW |
| dc.title | Experimental Demonstration of Reducing Source/Drain Resistance in In0.53Ga0.47As QW-MOSFETs through the Raised Source/Drain and Ultrathin Dielectric Insertion | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李敏鴻,陳敏璋,曾院介 | |
| dc.subject.keyword | 砷化銦鎵,量子井金氧半場效電晶體,源/汲極阻值,抬昇式源/汲極,接觸電阻率,蕭特基能障,費米能階釘札, | zh_TW |
| dc.subject.keyword | Indium gallium arsenide (In0.53Ga0.47As),quantum-well metal-oxide-semiconductor field-effect transistors (QW-MOSFETs),source/drain resistance,raised source/drain,Fermi-level pinning,Schottky barrier, | en |
| dc.relation.page | 121 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-08-07 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 機械工程學研究所 | zh_TW |
| 顯示於系所單位： | 機械工程學系 | |
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