由微波多層電路佈局圖中萃取集總元件數值

Abstract

本篇論文提出了一種計算用於電路佈局圖中集總元件數值的方法，透過該方法可快速的計算出指定的電感值與電容值，利用求出的電感值與電容值搭配電路佈局圖可以快速的檢查電路的正確性。而在計算過程中，由於一般電感與電容在佈局圖中會透過貫孔來連接，因此在在計算中必須考慮貫孔對電容與電感的影響。而在求出各電感值與電容值後，必須透過貫孔將各元件的兩端連接，以判定兩元件之間的連接關係，透過此方法建立元件連接表，並將其轉換成一般常見的電路圖模式，利用此電路圖可以搭配先前已完成的程式進行完整的電路驗證程序。

This thesis presents a method that extracts the values of elements from the layout of multi-layer microwave passive circuits. We can calculate the values of capacitance and inductance rapidly, and then check the correctness of the circuits by using calculated values. Because capacitance and inductance are connected by via in layouts, we must pay attention to the effect among them in the process. Therefore, we need to handle situations where elements are connected through vias after getting the values of these two. After that, we build the connection table and transfer it to a SPICE format circuit file. Finally, we can check the correctness between the circuit and the layout by using the program developed before.