請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60155
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃俊郎 | |
dc.contributor.author | Chih-Lung Hsiao | en |
dc.contributor.author | 蕭智隆 | zh_TW |
dc.date.accessioned | 2021-06-16T09:59:44Z | - |
dc.date.available | 2017-02-08 | |
dc.date.copyright | 2017-02-08 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-11-25 | |
dc.identifier.citation | [1] R. Syed, “RIC/DICMOS-Multi-Channel CMOS Formatter,” in International Test Conference, 2003, pp. 175-184.
[2] J. Park, et al. “Integration of Dual Channel Timing Formatter System for High Speed Memory Test Equipment,” in International SoC Design Conference, 2012, pp. 185-187. [3] L. Mostardini, L. Bacciarelli, L. Fanucci, L. Bertini, M. Tonarelli and M. D. Marinis, “FPGA-based Low-cost Automatic Test Equipment for Digital Integrated Circuits,” in International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2009, pp. 32-37. [4] Y.-Y. Chen, “An FPGA-based Sub-nanosecond Low-cost Timing Generator and Formatter,” M.S. thesis, National Taiwan University, Taipei, Taiwan, 2013. [5] P.-C. Shu, “A High Resolution and High Accuracy FPGA Formatter Prototype,” M.S. thesis, Nation Taiwan University, Taipei, Taiwan, 2014. [6] Analog Devices Inc. Quad Pin Timing Formatter ADATE207, 2007 [7] C. Y. Wang, Y. Y. Chen, J. L. Huang and X. L. Huang, “FPGA-Based Subset Sum Delay Lines,” 2014 IEEE 23rd Asian Test Symposium, 2014, pp. 287-291. [8] Chen, Y., Huang, J., Kuo, T., “Design and Implementation of an FPGA-Based Da-ta/Timing Formatter,” et al. J Electron Test, December 2015, Volume 31, Issue 5, pp 549–55 [9] C.-A. Lee, “Implementation of High-Resolution and Area-Efficient FPGA Pro-grammable Delay Lines,” M.S. thesis, Nation Taiwan University, Taipei, Taiwan, 2015. [10] Mariusz Suchenek, “Picosecond Resolution Programmable Delay Line,” in Meas-urement Science and Technology, 2009, Volume 20, pp. 1-5. [11] Daniel Costinett, Miguel Rodriguez, and Dragan Maksimovic , “Simple Digital Pulse Width Modulator Under 100 ps Resolution Using General-Purpose FPGAs,” in IEEE Transactions on Power Electronics, 2013, pp. 4466-4472. [12] David.C. Keezer, Te-HuiChen, Carl E. Gray, “Multi-Gigahertz Test Signal Synthe-sis with ‘Timing-on-the-Fly’,” in Mixed-Signal, Sensors and Systems Test Workshop, 2012, pp. 61-66. [13] Spartan-6 FPGA Configurable Logic Block, Xilinx, 2010. [14] Spartan-6 FPGA Block RAM Resources User Guide, Xilinx, 2011. [15] Spartan-6 Libraries Guide for HDL Designs, Xilinx, 2009. [16] Constraints Guide, Xilinx, 2012. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60155 | - |
dc.description.abstract | 格式器在自動測試機台中扮演重要的角色。其負責將測試向量、訊號格式及邊緣時序等資訊組合成測試訊號。ASIC格式器在市場上較為普遍,和FPGA格式器相比有較高的效能。因此,ASIC成為格式器的主流。然而,FPGA以其相對較低的開發成本、高設計靈活度以及不需要下線的優點,而有研究及發展的可能。
本論文提出的格式器實現在Xilinx Spartan-6 FPGA,支援多個區間的符號伸展與符號反轉功能。用硬體實現動態的(On-the-fly)符號伸展,讓格式器能在固定的系統時鐘(System clock)頻率的情形下,產生100、50、33.3、25 Msps的測試符號頻率的測試訊號。實驗結果顯示,提出的格式器能實現200 ps解析度的邊緣置放,其精確度為91 ps。 | zh_TW |
dc.description.abstract | The formatter plays an important role in automatic test equipment. It is responsible for formatting the test signal with test vectors, signal formats, edge timings and other input data. ASIC designed formatters are more common in the market comparing to ones with FPGA designed, since ASIC formatters achieve higher performance generally. For this reason, ASIC design is the mainstream for formatter. However, FPGA format-ters still have potential, because FPGA design has the advantages of lower development cost, higher flexibility, and no need to tape-out.
In this work, the proposed formatter is implemented on Xilinx Spartan-6 FPGA, and it is supported with multiple interval symbol-stretching and symbol inversion func-tions. On-the-fly symbol-stretching is achieve with hardware, and it empowers the for-matter to generate test signals with 100, 50, 33.3, 25 Msps symbol rate without changing the frequency of system clock. The measurement results show that the proposed for-matter achieves 200 ps edge placement resolution and the accuracy is 91 ps. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T09:59:44Z (GMT). No. of bitstreams: 1 ntu-105-R03943097-1.pdf: 3639185 bytes, checksum: b509d1361af86d347b3236bc5c203416 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv 目錄 v 圖目錄 vii 表目錄 x 第一章 緒論 1 1.1 研究動機與目的 1 1.2 相關研究 2 1.3 論文貢獻 3 1.4 論文架構 3 第二章 格式器之介紹與挑戰 4 2.1 自動測試機台 (ATE) 4 2.2 格式器 (Formatter) 5 2.3 符號產生器 (Symbol Generator, SG) 7 2.4 時間多工的符號生成 (Time-Multiplexed Symbols Generation) 11 第三章 所提出的FPGA格式器 12 3.1 系統架構 12 3.2 格式器架構 12 3.3 符號伸展與反轉技術 18 3.4 提出之延遲線與需求規格 22 3.5 查找表的建立與校正 25 第四章 實作與使用者介面 29 4.1 輸入檔案與波形資料的產生 29 4.2 格式器操作介面 30 第五章 實驗結果 32 5.1 系統規格與實驗配置 32 5.2 實驗流程 32 5.3 延遲線實現結果 33 5.4 邊緣置放範例 35 5.5 符號伸展與反轉波形範例 40 第六章 結論與未來研究方向 42 6.1 結論 42 6.2 未來研究方向 42 參考文獻 43 | |
dc.language.iso | zh-TW | |
dc.title | 基於現場可程式化邏輯閘陣列之支援符號伸展與反轉能力的高解析度格式器 | zh_TW |
dc.title | A High-Resolution FPGA Formatter with Symbol-Stretching and Inversion Capability | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 鄭國興,黃炫倫 | |
dc.subject.keyword | 測試機台,格式器,現場可程式化邏輯閘陣列,符號伸展,可程式化延遲線, | zh_TW |
dc.subject.keyword | test equipment,formatter,FPGA,symbol-stretching,programmable delay line, | en |
dc.relation.page | 44 | |
dc.identifier.doi | 10.6342/NTU201603765 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2016-11-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-105-1.pdf 目前未授權公開取用 | 3.55 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。