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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
dc.contributor.author | Cheng-Tang Chen | en |
dc.contributor.author | 陳正棠 | zh_TW |
dc.date.accessioned | 2021-06-16T09:55:40Z | - |
dc.date.available | 2020-08-24 | |
dc.date.copyright | 2020-08-24 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-08-18 | |
dc.identifier.citation | [1] G. E. Moore, “Cramming More Components onto Integrated Circuits,”Electronics, vol. 35, no. 8, pp. 114–117, Apr. 1965. [2] M. Schneider, “Automotive radar–status and trends,” Proc. German Microw. Conf., pp. 144–147, 2005. [3] H. Sakurai and Y. K. et al., “A 1.5GHz-modulation-range 10ms-modulation-period 180kHz rms frequency-error 26MHz-reference mixed-mode FMCW synthesizer for mm-wave radar application,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 292–293, Apr. 2011. [4] H. J. N. et al., “A DLL-Supported, Low Phase Noise Fractional-N PLL With a Wideband VCO and a Highly Linear Frequency Ramp Generator for FMCW Radars,”IEEE Transactions on Circuits and Systems, vol. 60, no. 12, pp. 3289–3302, July 2013. [5] B. Razavi, Design of Analog CMOS Integrated Circuits. MacGraw-Hill, second ed., 2017. [6] M. D. T. Michael H. Perrott and C. G. Sodini, “A Modeling Approach for Delta–Sigma Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis,”IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1028–1038, Aug. 2002. [7] J. Lee and Y.-A. L. et al., “A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2746–2756, Oct. 2010. [8] Y. L. et al., “A Fully Integrated 77GHz FMCW Radar System in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 216–217, Oct. 2010. [9] R. B. S. Wanghua Wu and J. R. Long, “A 56.4-to-63.4GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65nm CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1081–1096, Feb. 2014. [10] Y.-H. Kao and Y.-B. Hsieh, “A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial ATA Applications Using Two-Point Modulation,” IEEE Transactions on Electromagnetic Compatibility, vol. 51, no. 2, pp. 245–254, May 2015. [11] D. Dhar and P. van Zeijl et al., “Modeling and Analysis of The Effects of PLL Phase Noise on FMCW Radar Performance,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2017. [12] X. Chen and H.-S. K. et al., “An Analysis of Phase Noise Requirements for Ultra-Low-Power FSK Radios,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 37–40, July 2017. [13] H. Yeo and S. R. et al., “A 940MHz-Bandwidth 28.8μs-Period 8.9GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 238–239, Feb. 2016. [14] J. Lin and Z. S. et al., “A 77-GHz Mixed-Mode FMCW Signal Generator Based on Bang-Bang Phase Detector,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 2850–2863, Aug. 2018. [15] J. V. et al., “Multi-Band Linear Chirp Generation Based on a Type-III PLL,” in IEEE MTT-S International Microwave Symposium Digest (MTT), pp. 1–4, Jan. 2014. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60094 | - |
dc.description.abstract | 本篇論文提出一個5 GHz頻率調變連續波(Frequency-Modulated Con-tinuous Wave)訊號產生器。所提出之電路主要目標為在低中心頻率時產生更大的頻率調變範圍(Modulation Range),如此能在相同調變範圍下大幅降低功耗。採用以小數型鎖相迴路(Fractional-N Phase-locked Loop)為主的頻率合成器作為訊號產生器,此頻率合成器能以5 GHz為中心頻率調變700MHz(13.6%)的頻率範圍。一可變換極性之三階鎖相迴路(Type-3 PLL)被應用在本架構中,可有效改善在頻率轉折點和頻帶切換點的線性度。除此之外三階的架構亦可打破迴路頻寬對調變速度的限制。本論文提出透過切換頻帶控制電路(Switching Band Control circuit)和多組可變電容之LC壓控振盪器(Multi-varactor LC Voltage Control Oscillator)的組合來有效地提高輸出頻率的調變範圍,使頻率調變連續波雷達在距離的量測上能達到更高的準確度。本架構以台積電四十奈米互補式金氧半製程實現,所提出的頻率調變連續波訊號產生器總面積為1.96平方毫米而功耗則為3.2毫瓦。在鎖相迴路模式以5GHz為中心頻率,在相對於主頻率1 MHz的位置下所量測到的相位雜訊為-110 dBc/Hz。在頻率調變連續波模式以2.3 ms為週期調變700MHz的頻率下量測到的頻率誤差方均根值為625 kHz。 | zh_TW |
dc.description.abstract | This thesis presents a 5-GHz frequency-modulated continuous wave sig-nal generator(FMCW). The presented circuit aims to generate a wider fre-quency modulation range at low center frequency that grants significant ad-vantage at saving power. Utilizing a fractional-N phase-locked loop (PLL)-based synthesizer as the FMCW generator, the synthesizer modulates thecarrier frequency across a range of 700 MHz(13.6%). A Type-3 architec-ture with a switchable polarity is embedded to improve the linearity aroundthe chirp turning-around points (TAPs) and switching-bands points (SAPs).Moreover, Type-3 architecture break the trade-off between modulation slopeand PLL loop bandwidth. Switching Band Control (SBC) circuit and Multi-varactorLCVoltageControlOscillator(MV-VCO)areproposedasaefficientmethod to increase the modulation range so that the FMCW signal generatorcan achieve high resolution in distance detecting.FabricatedinTSMC40-nm1P10MCMOStechnology, theproposedsig-nal generator consume 3.2 mW power and occupies1.96mm2die area. Themeasured phase noise from 5 GHz carrier is -110 dBc/Hz at 1 MHz offset.Themeasuredroot-mean-square(rms)frequencyerrorofthegeneratedtrian-gle chirp over 1.15 ms period is 625 kHz. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T09:55:40Z (GMT). No. of bitstreams: 1 U0001-1308202014075800.pdf: 8523602 bytes, checksum: 22dd08f74dba8fbd2b3cedfc48dca878 (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | Acknowledgements ii 摘要iii Abstract iv 1 Introduction 1 1.1 Motivation and Research Goal . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Basic Concepts 4 2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Review of the classical PLL structure . . . . . . . . . . . . . . . . . . . 8 2.2.1 Introduction of the Type-2 PLL . . . . . . . . . . . . . . . . . . 8 2.2.2 A Linear Model for Type-2 Fractional-N PLL . . . . . . . . . . . 10 2.2.3 A Noise Model for Type-2 Fractional-N PLL . . . . . . . . . . . 11 2.3 Review of the One-Point Modulation Structure . . . . . . . . . . . . . . 13 2.4 Review of the Two-Point Modulation Structure . . . . . . . . . . . . . . 14 2.5 The Effect of PLL Phase Noise on FMCW Radar . . . . . . . . . . . . . 16 2.5.1 Range Correlation . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5.2 Phase Noise and RMS Frequency Error . . . . . . . . . . . . . . 18 3 Proposed Architecture 20 3.1 Proposed Type-3 FMCW synthesizer structure . . . . . . . . . . . . . . . 20 3.2 Locking Operation of the proposed Type-3 FMCW structure . . . . . . . 23 3.3 Challenge of a wide modulation range synthesizer . . . . . . . . . . . . . 24 4 Circuit Implementation 26 4.1 PFD with Polarity Controlled . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 OTA with Polarity Controlled . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 Switching Bands Control circuit . . . . . . . . . . . . . . . . . . . . . . 30 4.4 Multi-varactor VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 Programmable Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.6 MASH 1-1-1 Delta-Sigma modulator . . . . . . . . . . . . . . . . . . . 37 4.7 Ramp Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5 Noise Analysis and Behavior Simulation 39 5.1 Linear Noise Analysis of the Proposed Architecture . . . . . . . . . . . . 39 5.1.1 Noise Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.2 Overall Noise Analysis and Calculation . . . . . . . . . . . . . . 44 5.2 Behavior Simulation with MATLAB Script . . . . . . . . . . . . . . . . 48 5.3 Impact of Frequency Glitch on FMCW radar application . . . . . . . . . 49 6 Experimental Results 52 6.1 Print Circuit Board Design . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.2 Chip Area and Photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 Measurement Environment . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.5 Frequency Error and Power Consumption . . . . . . . . . . . . . . . . . 58 7 Conclusion 63 7.1 Thesis Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Bibliography 65 | |
dc.language.iso | en | |
dc.title | 一具有高輸出頻率範圍應用於連續頻率調變波雷達之三階頻率合成器 | zh_TW |
dc.title | A Type-3 Frequency-Modulated Continuous Wave RadarSynthesizer with Wide Frequency Modulation Range | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),劉深淵(Shen-Iuan Liu),陳巍仁(Wei-Zen Chen) | |
dc.subject.keyword | 鎖相迴路,連續頻率調變波雷達,分數型頻率合成器,高輸出頻率範圍, | zh_TW |
dc.subject.keyword | phase-locked loop,Frequency-ModulatedContinuousWaveRadar,fractional-N Synthesizer,wide modulation range, | en |
dc.relation.page | 66 | |
dc.identifier.doi | 10.6342/NTU202003245 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2020-08-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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