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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/59970完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
| dc.contributor.author | Kun-Wei Lin | en |
| dc.contributor.author | 林坤緯 | zh_TW |
| dc.date.accessioned | 2021-06-16T09:48:01Z | - |
| dc.date.available | 2017-02-16 | |
| dc.date.copyright | 2017-02-16 | |
| dc.date.issued | 2017 | |
| dc.date.submitted | 2017-01-23 | |
| dc.identifier.citation | [1] Krishnaswamy, A. B. Ma and P. Vishakantaiah, 'A study of bridging defect proba-bilities on a Pentium (TM) 4 CPU,' International Test Conference, pp. 688-695, 2001.
[2] B. Benware et al., 'Impact of multiple-detect test patterns on product quality,' In-ternational Test Conference, pp. 1031-1040, 2003. [3] X. Lin et al., 'Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects,' Asian Test Symposium, pp. 139-146, 2006. [4] A. F. Lin, K. Y. Liao, K. Y. Chiang and J. C. M. Li, 'TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects,' VLSI Design, Automation and Test, pp. 1-4, 2015. [5] A. K. Palaniswamy, S. Tragoudas and T. Haniotakis, 'ATPG for Delay Defects in Current Mode Threshold Logic Circuits,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 11, pp. 1903-1913, Nov. 2016. [6] M. Milir V., Kumar and S. Tragoudas, 'High-Quality Transition Fault ATPG for Small Delay Defects,' IEEE Transactions on Computer-Aided Design of Integrated Cir-cuits and Systems, vol. 26, no. 5, pp. 983-989, May 2007. [7] F. Hapke et al., 'Defect-oriented cell-aware ATPG and fault simulation for indus-trial cell libraries and designs,' International Test Conference, pp. 1-10, 2009. [8] J. Raik, R. Ubar, J. Sudbrock, W. Kuzmicz and W. Pleskacz, 'DOT: new determin-istic defect-oriented ATPG tool,' European Test Symposium, pp. 96-101, 2005. [9] A. Czutro, M. Sauer, T. Schubert, I. Polian and B. Becker, 'SAT-ATPG using pref-erences for improved detection of complex defect mechanisms,' VLSI Test Symposium, pp. 170-175, 2012. [10] D. Erb, K. Scheibler, M. Sauer and B. Becker, 'Efficient SMT-based ATPG for interconnect open defects,' Design, Automation & Test in Europe Conference & Exhibi-tion, pp. 1-6, 2014. [11] A. Touati; A. Bosio; P. Girard; A. Virazel; p. bernardi; M. Sonza Reorda; E. Au-vray, 'Scan-Chain Intra-Cell Aware Testing,' IEEE Transactions on Emerging Topics in Computing, no.99, pp.1-1, Nov. 2016. [12] K. Y. Liao, Sheng-Chang Hsu and J. C. M. Li, 'GPU-based N-detect transition fault ATPG,' Design Automation Conference, pp. 1-8, 2013. [13] Yu Huang, 'On N-detect pattern set optimization,' International Symposium on Quality Electronic Design, pp. 6 pp.-450, 2006. [14] K. R. Kantipudi and V. D. Agrawal, 'A Reduced Complexity Algorithm for Minimizing N-Detect Tests,' International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, pp. 492-497, 2007. [15] S. N. Neophytou and M. K. Michael, 'Test Pattern Generation of Relaxed n -Detect Test Sets,' IEEE Transactions on Very Large Scale Integration Systems, vol. 20, no. 3, pp. 410-423, March 2012. [16] S. Neophytou and M. K. Michael, 'On the Relaxation of n-detect Test Sets,' VLSI Test Symposium, pp. 187-192, 2008. [17] Y. T. Lin, O. Poku, N. K. Bhatti and R. D. Blanton, 'Physically-Aware N-Detect Test Pattern Selection,' Design, Automation and Test in Europe, pp. 634-639, 2008. [18] Y. T. Lin, C. U. Ezekwe and R. D. Blanton, 'Physically-Aware N-Detect Test Re-laxation,' VLSI Test Symposium, pp. 197-202, 2009. [19] Yen-Tzu Lin et al., 'Physically-Aware N -Detect Test,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 2, pp. 308-321, Feb. 2012. [20] Y. T. Lin, O. Poku, R. D. Blanton, P. Nigh, P. Lloyd and V. Iyengar, 'Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon,' International Test Conference, pp. 1-9, 2008. [21] J. E. Nelson, J. G. Brown, R. Desineni and R. D. Blanton, 'Multiple-detect ATPG based on physical neighborhoods,' Design Automation Conference, pp. 1099-1102, 2006. [22] S. Neophytou, M. K. Michael and K. Christou, 'Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning,' International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 401-409, 2009. [23] J. Geuzebroek, E. J. Marinissen, A. Majhi, A. Glowatz and F. Hapke, 'Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects,' Interna-tional Test Conference, pp. 1-10, 2007. [24] Sooryong Lee, B. Cobb, J. Dworak, M. R. Grimaila and M. R. Mercer, 'A new ATPG algorithm to limit test set size and achieve multiple detections of all faults,' De-sign, Automation and Test in Europe Conference and Exhibition, pp. 94-99, 2002. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/59970 | - |
| dc.description.abstract | 由於IC的設計複雜度增加以及特徵尺寸的縮小,簡單的錯誤模型 (fault model)已經無法偵測到足夠的缺陷 (defect)。
為了偵測更多的缺陷同時避免使用複雜的錯誤模型,偵測同個錯誤多次是一個可行的辦法,這是因為有些缺陷會在多次的錯誤偵測中恰巧被偵測到。Mentor graphics 提出了兩項計量 (metric) (BCE 和 FOC) 來衡量多次偵測圖樣對於現實電路缺陷的次是品質。 本篇論文中提出了一個平行化,搜尋空間分割 (search space partitioning) 的 N 次測試圖樣產生技術,考量了上述提到的兩項計量並且優化它們。動態的錯誤選擇 (Dynamic fault selection) 被用來提升 BCE 計量;在圖樣產生途中的測試選擇 (test selection) 則用來提升 FOC 計量。 本論文提出的方法在ISCAS89 和 ITC99 測試電路上進行驗證,實驗結果顯示,和Mentor Graphics 所提出的 N次測試自動化圖樣產生流程相比,本論文提出的方法可以達到更好的測試品質。 | zh_TW |
| dc.description.abstract | Due to the increasing design complexity and the shrinking feature size of the modern IC’s, the single-stuck-at fault model is no longer adequate of covering sufficient amount of defects.
To increase the defect coverage while avoiding using complex fault models, one solution is to detect each fault multiple times; by coincidental detections, the defect coverage is increased. Two metrics (BCE and FOC) are proposed by Mentor Graphics to estimate how well the multiple detect patterns can cover the real defects. In this thesis, a parallel, search-space partitioning N-detect ATPG methodology is proposed. The ATPG take the two multiple detect metric into consideration and aiming at improving the pattern quality according to them. Dynamic fault selection is used to increase the BCE metric and the test selection during ATPG is performed in favor of the FOC metric. The proposed techniques are validated using ISCAS89 and ITC99 benchmark cir-cuits. The experimental results show that the proposed techniques can achieve better pattern quality in terms of the two metrics comparing to the multiple detect ATPG flow proposed by Mentor Graphics. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T09:48:01Z (GMT). No. of bitstreams: 1 ntu-106-R03943149-1.pdf: 1197627 bytes, checksum: 1da624203f7de68f12f28bcd545a6e7a (MD5) Previous issue date: 2017 | en |
| dc.description.tableofcontents | 誌謝 I
ABSTRACT II 中文摘要 III TABLE OF CONTET IV LIST OF FIGURES VII LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Previous Works 1 1.3 Organization of the Thesis 3 CHAPTER 2 PRELIMINARIES 4 2.1 Bridging Fault Model 4 2.2 N-detect ATPG 4 2.2.1 N-detect ATPG Flow 4 2.2.2 N-detect ATPG Metrics 5 2.3 Search Space Partitioning ATPG 7 2.3.1 Overall Strategy 7 2.3.2 Memory Diagram 8 2.3.3 Splitting the search space 9 CHAPTER 3 PROPOSED PARALLEL N-DETECT ATPG 11 3.1 Overall Strategy 11 3.2 LDF Based Fault Selection 12 3.2.1 Motivation 12 3.2.2 Advantages and Drawbacks 12 3.3 Test Cube Scoring and Selection 13 3.3.1 Motivation 13 3.3.2 Test Cube Scoring 13 3.4 Techniques for Run Time Reduction 15 3.4.1 Motivation 15 3.4.2 Identifying and Handling ETD Faults 15 3.4.3 Identifying and Handling HTD Faults 16 3.4.4 Utilization of Spare Test Cubes 16 3.5 The detail scheme of parallel N-detect ATPG 19 CHAPTER 4 EXPERIMENT RESULTS 22 4.1 Experiment Result of N-detect ATPG in [2] 23 4.2 Proposed N-detect ATPG vs N-detect ATPG proposed in [2] 25 4.3 LDF Based Fault Selection 28 4.4 Scoring and Choosing Test Cubes 30 4.5 Identifying and Handling ETD and HTD Faults 33 4.5.1 Identifying and Handling ETD Faults 33 4.5.2 Identifying and Handling HTD Faults 37 4.6 Utilization of Spare Cubes 40 CHAPTER 5 CONCLUSIONS 44 REFERENCE 45 | |
| dc.language.iso | en | |
| dc.subject | N次測試自動化圖樣產生 | zh_TW |
| dc.subject | 多次測試 | zh_TW |
| dc.subject | 圖樣品質 | zh_TW |
| dc.subject | 搜尋空間分割平行測試圖樣產生 | zh_TW |
| dc.subject | 平行化程式設計 | zh_TW |
| dc.subject | search-space partitioning parallel ATPG | en |
| dc.subject | pattern quality | en |
| dc.subject | multiple detect | en |
| dc.subject | parallel programming | en |
| dc.subject | N-detect ATPG | en |
| dc.title | 針對改善圖樣品質之平行自動化N次測試圖樣產生方法 | zh_TW |
| dc.title | A parallel ATPG aiming at improving
N-detect pattern quality | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 呂學坤,李淑敏,黃炫倫 | |
| dc.subject.keyword | N次測試自動化圖樣產生,多次測試,圖樣品質,搜尋空間分割平行測試圖樣產生,平行化程式設計, | zh_TW |
| dc.subject.keyword | N-detect ATPG,multiple detect,pattern quality,search-space partitioning parallel ATPG,parallel programming, | en |
| dc.relation.page | 47 | |
| dc.identifier.doi | 10.6342/NTU201700175 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2017-01-23 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位: | 電子工程學研究所 | |
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