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???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
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dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
dc.contributor.author | Yu-Kai Wang | en |
dc.contributor.author | 王鈺凱 | zh_TW |
dc.date.accessioned | 2021-06-16T09:43:36Z | - |
dc.date.available | 2027-12-31 | |
dc.date.copyright | 2017-02-16 | |
dc.date.issued | 2017 | |
dc.date.submitted | 2017-01-30 | |
dc.identifier.citation | [1] C.-C. Tu, “Design of Low-Power Low Noise Analog Front-End Circuits for Biomedical Applications,” Master Thesis.
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Prabha et al., “A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications,” IEEE J. Solid-State Circuits, vol. 50, no. 8, pp. 1785–1795, Aug. 2015. [23] W. Jiang et al., “A ±50mV Linear-Input-Range VCO-Based Neural-Recording Front-End with Digital Nonlinearity Correction,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 484–486, Feb. 2016. [24] A. A. Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1803–1816, Aug. 2006. [25] Y. Tokunaga, S. Sakiyama, A. Matsumoto, and S. Dosho, “An On-Chip CMOS Relaxation Oscillator with Voltage Averaging Feedback,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1150–1158, Jun 2010. [26] A. A. Abidi and R. G. Meyer, “Noise in Relaxation Oscillators,” IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 794–802, Dec. 1983. [27] Y. Chae, K. Souri, and K. A. A. Makinwa, “A 6.3μW 20 Bit Incremental Zoom-ADC with 6 ppm INL and 1μV Offset,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3019–3027, Dec. 2013. [28] Anil K. Maini, Digital Electronics Principles, Devices and Applications, Wiley, 2007. [29] T.-H. Kuo, K.-D. Chen, and H.-R. Yeng, “A Wideband CMOS Sigma-Delta Modulator with Incremental Data Weighted Averaging,” IEEE J. Solid-State Circuits, vol. 37, no. 1, pp. 11–17, Jan. 2002. [30] R. Mohan et al., “A 0.6V 0.015mm2 Time-Based Biomedical Readout for Ambulatory Applications in 40nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 481–483, Feb. 2016. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/59893 | - |
dc.description.abstract | 及時的生理訊號感測在醫學臨床診斷上具有重要價值。隨著半導體工業的進步,使我們能將龐大的電路系統實現在單一晶片中。本論文著重探討應用於此系統之類比前端電路設計,此電路的主要任務為將振幅極小且低頻的生理信號直接轉換為數位訊號,同時維持訊號的完整度。但由於電路的直流偏移、閃爍雜訊與生醫訊號都落在低頻帶的範圍,因此訊號的品質容易受影響,故在本篇論文中使用截波器解決上述的問題。此外,傳統的類比訊號擷取電路由一個低雜訊放大器和一個類比數位轉換器組成,不論是在功率及面積方面都較沒效率,也增加了電路設計的複雜度。為了解決此問題,本篇採用電壓控制振盪器作為積分器的連續時間三角積分轉換器。
本論文實作並量測了兩個晶片,兩電路皆實作於台積電40奈米製程。第一個晶片實現了一個開路的電壓控制振盪器之類比前端電路,同時利用截波的技巧大幅降低來自電路的閃爍雜訊,核心晶片面積僅0.0145 mm2,為與目前相關文獻相比的最小晶片面積,同時維持50 dB的信號與雜訊比(頻寬為5 kHz)。然而此電路為開路的操作,最大的輸入信號會受到電壓控制振盪器的非線性所限制。在第二個晶片裡,我們延續使用電壓控制振盪器作為積分器及截波的技巧,並利用電容式的數位類比轉換器作回授,降低電壓控制振盪器的輸入振幅,大幅擴大電路的動態範圍到74.9 dB(頻寬為2 kHz),在品質因素方面達到FoMs = 150 dB及FoMw = 1.16 pJ/conv,皆達到與相關文獻相比下的最好的品質因素。以上兩個晶片皆能符合生醫前端電路的需求,並且在能量效率及晶片面積上皆有很突出的表現。 | zh_TW |
dc.description.abstract | Real-time biomedical signal acquisition is very crucial in modern diagnostics. Thanks to the development of microelectronics, it is possible to integrate the bulky system into a single chip. In this thesis, we will discuss the design of an analog front-end (AFE) which converts the weak analog signal into digital signal for biomedical applications while maintains signal integrity. Since the target signal, offset and flicker noise are all in the low-frequency range, the signal is susceptible to these non-idealities. To solve this problem, we apply chopping technique in this thesis. Additionally, conventional AFE system is composed of a low-noise amplifier and an ADC, which makes it not power/area efficient and also increases the circuit complexity. Our solution to this problem is applying a voltage-controlled oscillator (VCO) -based continuous-time delta-sigma modulator (CTDSM).
Two circuits are implemented and verified, both of them are fabricated in TSMC 40 nm process. The first one realizes a chopped open-loop VCO-based AFE that only takes the area of 0.0145 mm2 which is the smallest chip compared to the relative AFE references while maintains SNR of 50 dB (with the bandwidth of 5 kHz). However, due to the open-loop behavior, the dynamic range is limited by VCO non-linearity. In the second circuit, we apply a VCO-based integrator, chopper, and a capacitive-feedback DAC. With the capacitive-feedback DAC the amplitude of VCO input is decreased and the dynamic range is increased to 74.9 dB (with the bandwidth of 2 kHz). The figure of merits (FoM) FoMs = 150 dB and FoMw = 1.16 pJ/conv are shown respectively. Both of them reach the best FoM compared to the state-of-the-art of relative applications. These chips are not only suitable for biomedical applications but also reach great performances in power efficiency and chip area. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T09:43:36Z (GMT). No. of bitstreams: 1 ntu-106-R03943014-1.pdf: 7441057 bytes, checksum: e72aa95e6550e2a83eafb62ed98e88ab (MD5) Previous issue date: 2017 | en |
dc.description.tableofcontents | List of Figures xiii
List of Tables xvii Chapter 1 Introduction 1 1.1 Background 1 1.2 Dissertation Overview 3 Chapter 2 Fundamentals of Implementation Amplifiers 5 2.1 Fundamentals of Bio-Potential Sensor Read-Out Systems 5 2.2 Architectures of IA circuits 5 2.2.1 3-OPAMP IA 6 2.2.2 Current-Feedback IA 6 2.2.3 Capcitively-Coupled IA 7 2.3 Non-Idealities in Bio-Potential Sensing System 8 2.3.1 Offset Voltage 8 2.3.2 Noise 11 2.4 Chopping 13 2.5 Analyzing Noise in CCIA with Chopper 15 2.6 Summary 17 Chapter 3 Fundamentals of Delta-Sigma Modulators and AFE Circuit Design 19 3.1 Introduction 19 3.2 Introduction to Delta-Sigma Modulator 19 3.3 AFE with IA and ADC 21 3.3.1 Conventional AFE 21 3.3.2 IA and ADC Combined AFE 24 3.4 Summary 27 Chapter 4 Design of Open-Loop VCO-based CTDSM AFE 29 4.1 Introduction 29 4.2 Proposed System Block Diagram 30 4.3 VCO-Based Integrator 31 4.3.1 Introduction to VCO as Integrator 32 4.3.2 Ring Oscillators 34 4.3.3 Relaxation Oscillators 35 4.4 Proposed VCO-Based CTDSM AFE 36 4.4.1 System Architecture 36 4.4.2 Proposed Chopped VCO 37 4.4.3 Noise Analysis 40 4.4.4 Processing Circuit 43 4.5 Simulated and Measured Results 44 4.5.1 Simulated Results 44 4.5.2 Measurement Results 47 4.6 Summary 52 Chapter 5 Design of Closed-Loop VCO-based CTDSM AFE 53 5.1 Introduction 53 5.2 Proposed Closed Loop VCO-Based CTDSM AFE 54 5.2.1 System Architecture 54 5.2.2 Proposed Chopped VCO 56 5.2.3 Noise Analysis 57 5.2.4 Quantizer Design 57 5.2.5 DAC and DEM Design 61 5.3 Simulated and Measured Results 66 5.3.1 Simulation Results 66 5.3.2 Measurement Results 70 5.4 Summary 74 Chapter 6 Conclusions and Future Works 75 6.1 Conclusions 75 6.2 Future Works 75 References 77 | |
dc.language.iso | en | |
dc.title | 應用於生醫感測系統之電壓控制振盪器的連續時間三角積分類比前端電路設計 | zh_TW |
dc.title | Design of Voltage-Controlled Oscillator Based Continuous-Time Delta-Sigma Analog Front-End Circuits for Biomedical Applications | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),李泰成(Tai-Cheng Lee),林永裕(Yung-Yu Lin) | |
dc.subject.keyword | 生醫感測器,電壓控制振盪器,三角積分轉換器, | zh_TW |
dc.subject.keyword | bio-potential sensor,voltage-controlled oscillator,delta-sigma modulator, | en |
dc.relation.page | 80 | |
dc.identifier.doi | 10.6342/NTU201700283 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2017-02-03 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
Appears in Collections: | 電子工程學研究所 |
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