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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58887完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | |
| dc.contributor.author | Chia-Hao Hsu | en |
| dc.contributor.author | 許家豪 | zh_TW |
| dc.date.accessioned | 2021-06-16T08:36:50Z | - |
| dc.date.available | 2018-11-05 | |
| dc.date.copyright | 2013-11-05 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-10-29 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58887 | - |
| dc.description.abstract | 本論文提出一個基於相位偵測的低雜訊比較器使用在子範圍類比數位轉換器。可以減低熱雜訊並且有較低機率發生亞穩態的特性。一個十位元的子範圍類比數位轉換器由3.9位元的快閃類比數位轉換器和7位元的循序漸近式類比數位轉換器組成。本論文提出的類比數位轉換器使用台積電的40奈米低功耗製程製做完成。此類比數位轉換器達到54.41dB訊號雜訊失真比，操作在160MHz的取樣頻率。在1.1V的電源供應下消耗2.7mW。品值因素達到39.4fJ/convertion-step。核心電路面積佔據0.0475平方毫米。 | zh_TW |
| dc.description.abstract | A low-noise phase-detector-based (PD-based) comparator is proposed for subrange analog-to-digital converters (ADCs) in this thesis. It can reduce the thermal-induced noise as well as the probability of the metastability. The 10-bit subrange ADC is composed of a 3.9-bit flash ADC and a 7-bit SAR ADC. The proposed ADC was fabricated in a 40-nm LP CMOS technology. The ADC achieves 54.41-dB SNDR at 160MS/s under a 1.1V supply voltage and consumes 2.7mW. The figure-of-merit (FOM) is 39.4 fJ/conversion-step. The active area is 0.0475 mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T08:36:50Z (GMT). No. of bitstreams: 1 ntu-102-R99943127-1.pdf: 8762039 bytes, checksum: fccd0dca5d10bf422efedf88713546b6 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 摘要 i
Abstract ii Contents iii List of Figures vii List of Tables xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 1 Chapter 2 Fundamentals of ADCs 3 2.1 Introduction 3 2.2 ADC Performance Metrics 3 2.2.1 Differential and Integral Nonlinearity (DNL, INL) 3 2.2.2 Signal-to-Noise Ratio (SNR) 6 2.2.3 Signal-to-Noise-and-Distortion Ratio (SNDR) 8 2.2.4 Effective Number-of-Bits (ENOB) 8 2.2.5 Spurious-Free Dynamic Range (SFDR) 8 2.2.6 Figure of Merit (FoM) 9 2.3 Architectures of Analog-to-Digital Converters 10 2.3.1 Flash ADC 10 2.3.2 Subrange ADC 11 2.3.3 Successive Approximation ADC 12 Chapter 3 Subrange ADC with PD-based comparator 15 3.1 Introduction 15 3.2 Asynchronous SAR ADC 15 3.3 Metastability of asynchronous SAR ADC 16 3.4 Proposed phase-detector-based comparator. 19 3.4.1 Principle 19 3.4.2 Circuit description 22 3.4.3 Noise analysis 28 3.5 Subrange ADC with PD-based comparator 33 3.6 Summary 40 Chapter 4 Circuit Implementation 41 4.1 Introduction 41 4.2 Bootstrapped switch 41 4.3 Flash comparator 42 4.4 Data register 44 4.5 Capacitive DAC 46 4.6 Clock Generator 49 4.7 Post-Layout Simulation 50 4.8 Summary 51 Chapter 5 Experimental Results 53 5.1 Introduction 53 5.2 Print Circuit Board Design 53 5.3 Measurement Setup 54 5.4 Measurement Results 55 5.4.1 10-bit subrange ADC 55 5.4.2 PD-based comparator 64 5.5 Summary 67 5.6 Conclusions 68 5.7 Future Works 69 Bibliography 71 | |
| dc.language.iso | en | |
| dc.subject | 亞穩態 | zh_TW |
| dc.subject | 基於相位偵測的低雜訊比較器 | zh_TW |
| dc.subject | 子範圍類比數位轉換器 | zh_TW |
| dc.subject | Metastability | en |
| dc.subject | Phase-detector -based comparator | en |
| dc.subject | Subrange ADC | en |
| dc.title | 一個十位元高速的子範圍類比數位轉換器 | zh_TW |
| dc.title | A 10-bit High-Speed Subrange ADC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 洪浩喬,陳信樹 | |
| dc.subject.keyword | 亞穩態,基於相位偵測的低雜訊比較器,子範圍類比數位轉換器, | zh_TW |
| dc.subject.keyword | Metastability,Phase-detector -based comparator,Subrange ADC, | en |
| dc.relation.page | 75 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-10-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-102-1.pdf 未授權公開取用 | 8.56 MB | Adobe PDF |
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