請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58852
標題: | 具適應性負載暫態響應提升技術的電流模式降壓型轉換器之設計與實現 Design and Implementation of the Current Mode Buck Converter with Adaptive Load Transient Enhancement Techniques |
作者: | Bor-Tsang Hwang 黃柏蒼 |
指導教授: | 陳中平 |
關鍵字: | 降壓型轉換器,電流模式控制,暫態響應,電流泵,補償電路, buck converter,current mode control,transient response,current pump,compensation circuit, |
出版年 : | 2013 |
學位: | 碩士 |
摘要: | 隨著製程的演進,信號擺幅以及供應電壓持續的降低。因此,今日的電壓調節器必需在負載變動時能做出快速的反應並且維持穩定的輸出電壓。傳統的電流模式降壓型轉換器,由於頻寬上的限制無法擁有快速的暫態響應。在本論文中我們提出兩個新的架構來改善這個問題。
在切換式轉換器中,由於電感的限制電流無法立即改變,因此有文獻提出使用輸出電流泵的方式,在暫態時來補償電感電流與輸出電流的落差。然而這個架構無法直接適用於電流模式降壓型轉換器上。在第一顆晶片中,我們針對這個架構進行修正,提出適應性雙電流泵的方式。由於輸出電流泵會影響到原本迴路的運作,我們使用另一電流泵去彌補這個方式對於補償電路上的影響。這個架構被實現於TSMC 0.35μm CMOS製程。量測結果顯示暫態響應的回復時間約為2.8~4 μs。相較於傳統架構而言,回復時間被減少了約75%。另外,在輸出電流介於120~600 mA間,轉換效率皆大於82 %;與傳統架構相比,這個架構所造成的效率衰減皆小於0.3%。 在第二顆晶片中,我們使用動態調整補償電路電壓的方式。在電流模式控制中,補償電容上的電壓需要隨不同負載而有所變動。因此,藉由將電感電流的資訊加到補償電路的輸出上,使得當不同負載時補償電容所需的電壓變動量較傳統架構減少,藉此來達到較快的反應速度。這個架構被實現於TSMC 0.25μm CMOS製程。佈局後模擬顯示其暫態響應的回復時間約為3~6 μs。而實現這個架構所需要增加的面積約為57.5k μm2,遠較前一個架構所需要增加的面積小(333k μm2)。另外,在輸出電流介於100~500 mA間,轉換效率皆大於90%;與傳統架構相比,這個架構所造成的效率衰減皆小於0.4%。 With the evolution of the process, the supply voltage and the signal level decreases. Therefore, fast load transient response to keep output voltage stable and clean becomes very critical for voltage regulators nowadays. Traditional current mode buck converter cannot attain fast transient response due to bandwidth limitations. In this thesis, we propose two new architectures to improve this problem. The output current slew rate of switching converters is restricted by the inductor. Therefore, the additional current pump is proposed in the literature to provide the insufficient current between the inductor and the output load when loading is changed suddenly. However, this architecture cannot apply to the current mode buck converters directly. In the first chip, we modify this architecture and adopt the adaptive dual current pump technique. Since the output current pump will affect the operation of the original loop, the other current pump is added to make up its impact on the compensation circuit. This technique is implemented with TSMC 0.35μm CMOS process. Measurement results show the recovery time is within 2.8~4 μs. Compared with conventional design, the performance of recovery time is reduced by about 75%. In addition, power conversion efficiency is larger than 82% with load current between 120 mA and 600 mA in proposed architecture. Efficiency degradation is less than 0.3% compared with conventional architecture. In the second chip, we use the dynamic voltage adjustment of the compensation circuit technique. In current mode control, the voltage of the compensation capacitor needs to be changed according to different load conditions. By adding the inductor current signal to the output of the compensation circuit, the voltage difference of the compensation capacitor at different loads can be reduced. As a result, faster transient response is obtained. This technique is implemented with TSMC 0.25μm CMOS process. Post-layout simulation results show the recovery time is within 3~6 μs. The additional area for implementing this technique is 57.5k μm2, which is much smaller than the previous technique (333k μm2). In addition, power conversion efficiency is larger than 90 % with load current between 100 mA and 500 mA in proposed architecture. Efficiency degradation is less than 0.4% compared with conventional architecture. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58852 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-102-1.pdf 目前未授權公開取用 | 5.41 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。