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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 闕志達(Tzi-Dar Chiueh) | |
dc.contributor.author | Che-Min Huang | en |
dc.contributor.author | 黃哲銘 | zh_TW |
dc.date.accessioned | 2021-06-16T08:34:00Z | - |
dc.date.available | 2017-03-18 | |
dc.date.copyright | 2014-03-18 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-12-02 | |
dc.identifier.citation | 參考資料
[1] Alice Wang, Anantha P. Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology,” IEEE Journal of Solid-State Circuits, vol.40, no.1, pp.310-319, Jan. 2005. [2] A. Khandekar, N. Bhushan, T. Ji and V. Vanghi, “Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits,” IEEE Journal of Solid-State Circuits, vol.40, no.9, pp.1778-1786, Sept. 2005. [3] Myeong-Eun Hwang, A. Raychowdhury, Keejong Kim, K. Roy, “A 85mV 40nW Process-Tolerant Subthreshold 8x8 FIR Filter in 130nm Technology,” IEEE Symposium on VLSI Circuits, June 2007. [4] M. Miyazaki, J. Kao, Anantha P. Chandrakasan, “A 175mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture,” IEEE International Solid-State Circuits Conference, Feb. 2002. [5] Benton H. Calhoun, Anantha P. Chandrakasan, “Ultra-Dynamic Voltage Scaling Using Subthreshold Operation and Local Voltage Dithering in 90nm CMOS,” International Solid-State Circuits Conference, Feb. 2005. [6] Vivienne Sze, Anantha P. Chandrakasan, “A 0.4-V UWB Baseband Processor,” ACM/IEEE International Symposium on Low Power Electronics and Design, Aug. 2007. [7] Yogesh K. Ramadass, Anantha P. Chandrakasan, “Minimum Energy Tracking Loop with Embedded DC-DC Converter Delivering Voltages down to 250mV in 65nm CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2007. [8] JoyceJoyce Kwong, Yogesh K. Ramadass, Naveen Verma, Anantha P. Chandrakasan, “A 65nm sub-vt Microcontroller with Integrated SRAM and Switched Capacitor DC-DC Converter,” IEEE Journal of Solid-State Circuits, , vol.44, no.1, pp.115,126, Jan. 2009. [9] N. Ickes, G. Gammie, M.E. Sinangil, R. Rithe, J. Gu, A. Wang, H. Mair, S. Datla, B. Rong, S. Honnavara-Prasad, L. Ho, G. Baldwin, D. Buss, Anantha P. Chandrakasan, Uming Ko, “A 28nm 0.6V Low-Power DSP for Mobile Applications,” IEEE Journal of Solid-State Circuits, vol.47, no.1, pp.35,46, Jan. 2012. [10] Sven Luetkemeier, Thorsten Jungeblut, Mario Porrmann, Ulrich Rueckert, “A 200mV 32b Subthreshold Processor with Adaptive Supply Voltage Control,” IEEE International Solid-State Circuits Conference, Feb. 2012. [11] S. Jain, S. Khare, S. Yada, Ambili V, P. Salihundam, S. Ramani, S. Muthukumar, Srinivasan M, A. Kumar, S. Kumar Gb, R. Ramanarayanan, V. Erraguntla, J. Howard, S. Vangal, S. Dighe, G. Ruhl, P. Aseron, H. Wilson, N. Borkar, Vivek De, S. Borkar, “A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor in 32nm CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2012. [12] R. Pawlowski, E. Krimer, J. Crop, J. Postman, N. Moezzi-Madani, M. Erez, P. Chiang, “A 530mV 10-Lane SIMD Processor with Variation Resiliency in 45nm SOI,” IEEE International Solid-State Circuits Conference, Feb. 2012. [13] A. Agarwal, S. K Mathew, S. K Hsu, M. A Anders, H. Kaul, F. Sheikh, R. Ramanarayanan, S. Srinivasan, R. Krishnamurthy, S. Borkar, “A 320mV-to-1.2V On-Die Fine-Grained Reconfigurable Fabric for DSP Media Accelerators in 32nm CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2010. [14] Y. Pu, J. P. de Gyvez, H. Corporaal, Y. Ha, “An Ultra-Low-Energy_Frame Multi-Standard JPEG Co-Processor in 65nm CMOS with Sub_Near-Threshold Power Supply,” IEEE International Solid-State Circuits Conference, Feb. 2010. [15] T.-J. Lin, C.-A. Chien, P.-Y. Chang, C.-W. Chen, P.-H. Wang, T.-Y. Shyu, C.-Y. Chou, S.-C. Luo, J.-I. Guo, T.-F. Chen, G. C.H. Chuang, Y.-H. Chu, L.-C. Cheng, H.-M. Su, C. Jou, M. Ieong, C.-W. Wu, J.-S. Wang, “A 0.48V 0.57nJ per Pixel Video-Recording SoC in 65nm CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2013. [16] D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, D. Sylvester, “A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2013. [17] J.-S. Chen, C. Yeh, J.-S. Wang, “Self-Super-Cutoff Power Gating with State Retention on a 0.3V 0.29fJ per Cycle per Gate 32b RISC Core in 0.13um CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2013. [18] M. Konijnenburg, Y. Cho, M. Ashouei, T. Gemmeke, C. Kim, J. Hulzink, J. Stuyt, M. Jung, J. Huisken, S. Ryu, J. Kim, H. de Groot, “Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2013. [19] S. Kim, I. Kwon, D. Fick, M. Kim, Y.-P. Chen, D. Sylvester, “Razor-Lite: A Side-Channel Error-Detection Register for Timing-Margin Recovery in 45nm SOI CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2013. [20] T.-H. Kim, J. Liu, C.H. Kim, “An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement,” IEEE Custom Integrated Circuits Conference, Sept. 2007. [21] J.-S. Wang, K.-J. Chang, S.-Y. Yang, T.-H. Hsieh, C. Yeh, “RSCE-aware ultra-low-voltage 40-nm CMOS circuits,” International SoC Design Conference, Nov. 2011. [22] T.-H. Kim, J. Keane, H. Eom, C.H. Kim, “Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design,” IEEE Transactions on Very Large Scale Integration Systems, vol.15, no.7, pp.821,829, July 2007. [23] D. Ernst, N.-S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, T. Mudge, “Razor: a low-power pipeline based on circuit-level timing speculation, IEEE/ACM International Symposium on Microarchitecture, Dec. 2003. [24] T. Sato, Y. Kunitake, “A Simple Flip-Flop Circuit for Typical-Case Designs for DFM,” International Symposium on Quality Electronic Design, March 2007. [25] M. Agarwal, B.C. Paul, M. Zhang, S. Mitra, “Circuit Failure Prediction and Its Application to Transistor Aging,” IEEE VLSI Test Symposium, May 2007. [26] K.A. Bowman, J.W. Tschanz, N.-S. Kim, J.C. Lee, C.B. Wilkerson, S.L. Lu, T. Karnik, V.K. De, “Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance,” IEEE Journal of Solid-State Circuits, vol.44, no.1, pp.49,63, Jan. 2009. [27] S.J. Dillen, D.A. Priore, A.K. Horiuchi, S.D. Naffziger, “Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules,” IEEE Custom Integrated Circuits Conference, Sept. 2012. [28] M. Kurimoto, H. Suzuki, R. Akiyama, T. Yamanaka, H. Ohkuma, H. Takata, H. Shinohara, “Phase-adjustable Error Detection Flip-Flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling,” ACM/IEEE Design Automation Conference, June 2008. [29] Y.-M. Yang, H.-R. Jiang, S.-T. Ho, “PushPull: short path padding for timing error resilient circuits,” ACM international symposium on International symposium on physical design, March 2013 [30] Aeroflex Gaisler official website http://www.gaisler.com/index.php/products/processors/leon3 [31] GRLIB IP Core User's Manual [32] O. Marvin, S.-M. Jose, “Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip”, Chapter 2, Process Variation Challenges and Solutions Approaches, 2012. [33] Rahul Rao, A. Jenkins, J.-J. Kim, T. J. Watson, “A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement,” IEEE International Solid-State Circuits Conference, Feb. 2008. [34] J. Zhou, S. Jayapal, B. Busze, L. Huang, J. Stuyt, “A 40nm Dual-Width Standard Cell Library for Near_Sub-Threshold Operation,” IEEE Transactions on Circuits and Systems—I: REGULAR PAPERS, VOL. 59, NO. 11, NOVEMBER 2012. [35] M. J. Turnquist, E. Laulainen, J. Makipaa, M. Pulkkinen, L. Koskinen, “Measurement of a Timing Error Detection Latch Capable of Sub-threshold Operation,” NORCHIP, Nov. 2009. [36] M. J. Turnquist, E. Laulainen, J. Makipaa, L. Koskinen, “Measurement of a System-Adaptive Error-Detection Sequential Circuit with Subthreshold SCL,” NORCHIP, Nov. 2011. [37] K. Chae, C.-H. Lee, S. Mukhopadhyay, “Timing error prevention using elastic clocking,” IEEE International Conference on IC Design & Technology (ICICDT), May 2011. [38] M. Choudhury, V. Chandra, K. Mohanram, R. Aitken, “TIMBER: Time borrowing and error relaying for online timing error resilience,” Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2010. [39] V. Joshi, D. Blaauw, D. Sylvester, “Soft-Edge Flip-flops for Improved Timing Yield: Design and Optimization,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2007. [40] Y.-S. Su, P.-H. Chang, S.-C. Chang and T.-T. Hwang, “Synthesis of a Timing-Error Detection Architecture,” IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2008. [41] S. Das, C. Tokunaga, S. Pant, W.-H. Ma, S. Kalaiselvan, K. Lai, D.M. Bull, D.T. Blaauw, “RazorII: In Situ Error Detection and Correction for PVT ane SER Tolerance,” IEEE Journal of Solid-State Circuits, Jan. 2009. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58839 | - |
dc.description.abstract | 由於消費者的需求,目前手持式裝置的功能愈來愈強大,然而有限的電池容量無法因應耗電量過大的問題;根據裝置目前所需的效能需求,使用動態電壓頻率調整的技術可以有效降低能源消耗,但在愈來愈先進的製程中,因為電晶體面積及臨界電壓的下降,變異的發生將更嚴重影響電路效能,甚至使電路失效。
本論文設計了一個能操作在0.4v的元件庫,能夠確保在低電壓操作下邏輯的正確性。而為了因應低電壓下變異對電路造成的影響,本論文提出了時序錯誤復原正反器,能夠使變異對電路造成的影響被消除,進而提升電路的效能。模擬結果顯示所提出的方法在各個測試電路,包括Leon3處理器中都能得到更佳的能源的使用效率。 | zh_TW |
dc.description.abstract | Due to demands of consumers, handheld devices are more and more powerful. However, limited energy capacitance cannot afford this energy budget. According to the performance needed now, dynamic voltage frequency scaling (DVFS) can efficiently lowering the energy consumption. But in the advanced technology node, transistor size and threshold voltage are so small that variation can cause serious impact in circuits performance or functionality.
This thesis design a low-voltage cell library, and make sure the integrity of cells when operating at 0.4 volt. This thesis also proposes timing error resilient flip-flop to mitigate the impact of variation, so that the performance of circuits can be improved. The simulation results show that the proposed method can get better energy efficiency in benchmarks and Leon3 processor. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T08:34:00Z (GMT). No. of bitstreams: 1 ntu-102-R00943158-1.pdf: 12132394 bytes, checksum: 35780e373c5490555b24239bbc413e7d (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | 目錄
誌謝…………………………………………………………………..…………..III 摘要……………………………………………………………….……..………...V Abstract…………………………………………………………………….…...VII 目錄………………………………………………………………….……….…...IX 圖目錄……………………………….…………………………….……...……... XI 表目錄……………………………….…………………………….…...….…... XIII 1. 第一章 緒論 1 1.1 研究背景 1 1.2 研究動機 1 1.3 論文架構 2 2. 第二章 寬廣操作電壓電路設計挑戰 3 2.1 能源效益最佳化的操作電壓 3 2.2 電路設計時的變異來源 5 2.2.1 製程、電壓、溫度變異(PVT variation): 6 2.2.2 老化效應(aging effect) 7 2.3 變異對電路所造成的影響 8 2.3.1 功能錯誤 8 2.3.2 時序錯誤 9 3. 第三章 時序錯誤偵測及更正 11 3.1 時序錯誤偵測及更正方法分析 12 3.2 時鐘信號週期借用 13 3.3 短路徑問題及解決方法 16 3.4 時鐘信號週期借用的時序說明 18 3.5 電路的架構限制 20 4. 第四章 低電壓操作元件庫設計 22 4.1 設計目標 22 4.1.1 設計前分析 22 4.1.2 靜態雜訊邊界 25 4.1.3 設計步驟 28 4.2 元件庫設計結果 34 4.3 結果比較 43 5. 第五章 時序錯誤復原正反器設計 44 5.1 時序錯誤復原正反器架構 44 5.2 時序錯誤的偵測及修正 46 5.3 文獻中之錯誤偵測及更正之電路設計 48 5.4 時序錯誤偵測及更正電路模擬結果與比較 52 5.5 使用ISCAS89 benchmark模擬結果比較 53 5.5.1 ISCAS89 benchmark簡介 54 5.5.2 模擬結果與比較 55 5.5.3 蒙地卡羅(Monte-Carlo)模擬分析 63 6. 第六章 Leon3處理器實作模擬 69 6.1 Leon3處理器簡介 69 6.2 模擬結果與比較 71 6.3 蒙地卡羅(Monte-Carlo)模擬分析 82 7. 第七章 結論與展望 87 8. 參考資料 89 圖目錄 圖 2 1 電路設計操作電壓變化趨勢 3 圖 2 2 能源效率最佳的操作電壓示意圖 5 圖 2 3 廣域性製程變異及區域性製程變異[33] 7 圖 2 4 電路錯誤範例[9] 9 圖 2 5 變異所造成的時序錯誤 10 圖 3 1 預留部份時鐘信號週期以防止變異造成電路錯誤[19] 11 圖 3 2 週期借用範例 14 圖 3 3 傳統設計概念與時鐘信號週期借用設計概念差別 15 圖 3 4 Soft Edge Flip-Flop與Transparency window說明 15 圖 3 5 短路徑問題的限制 16 圖 3 6 以加法器為例說明短路徑問題以及解決方式 17 圖 3 7 時鐘信號週期借用時序說明 19 圖 3 8 過於規律的電路示意圖 21 圖 3 9 最長路徑迴路示意圖 21 圖 4 1 ARM Cortex-M3 分析[19] 23 圖 4 2 逆短通道效應 25 圖 4 3 雜訊邊界檢測方法 26 圖 4 4 雜訊邊界檢測範例 27 圖 4 5 標準元件庫設計步驟 28 圖 4 6 邏輯閘設計步驟說明 29 圖 4 7 反向器靜態雜訊邊界分析 30 圖 4 8 反相器靜態雜訊邊界分析投影 30 圖 4 9 反相器延遲時間分析 31 圖 4 10 反相器延遲時間分析投影 31 圖 4 11 反相器功率消耗分析 32 圖 4 12 反相器功率消耗分析投影 32 圖 4 13 反相器功率及延遲時間乘積分析 33 圖 4 14 反相器功率及延遲時間乘積投影 33 圖 5 1 時序錯誤復原正反器架構 44 圖 5 2 時序錯誤復原正反器操作波形示意圖 46 圖 5 3 時序錯誤復原正反器模擬波形 47 圖 5 4 時序錯誤復原正反器於0.4v下1000次模擬結果 47 圖 5 5 Razor Flip-Flop 電路架構 48 圖 5 6 Razor Flip-Flop II 電路架構 49 圖 5 7 DSTB電路架構 50 圖 5 8 TDTB電路架構 50 圖 5 9 SEF電路架構 51 圖 5 10 Benchmark s386比較 56 圖 5 11 Benchmark s349比較 58 圖 5 12 Benchmark s1196比較 59 圖 5 13 s1196中路徑延遲時間的分佈 60 圖 5 14 各種時序電路架構在測試電路中比較表 62 圖 5 15 低電壓下s1196電路蒙地卡羅實驗後比較 68 圖 6 1 Leon3 Block Diagram 69 圖 6 2 Leon3整數運算單元架構圖 70 圖 6 3 Leon3延遲路徑分佈圖 71 圖 6 4 Leon3模擬波型圖 72 圖 6 5 於1.0v下時序錯誤偵測與更正電路模擬結果 74 圖 6 6 於1.0v時時序錯誤偵測及更正電路功率比較 77 圖 6 7 於時脈1000M下時序錯誤偵測及更正電路功耗比較 77 圖 6 8 於0.7v下時序錯誤偵測與更正電路模擬結果 78 圖 6 9 於0.7v下時序錯誤偵測及更正電路功率比較 79 圖 6 10 於時脈550M下時序錯誤偵測及更正電路功耗比較 79 圖 6 11 於0.4v下時序錯誤偵測與更正電路模擬結果 80 圖 6 12 於0.4v下時序錯誤偵測及更正電路功率比較 81 圖 6 13 於時脈550M下時序錯誤偵測及更正電路功耗比較 81 圖 6 14 於0.3v下時序錯誤偵測及更正電路功率比較 84 圖 6 15 於0.3v下蒙地卡羅實驗後最高操作時脈下PDP比較 85 圖 6 16 於0.3v下蒙地卡羅實驗後最高操作時脈下EDP比較 86 表目錄 表格 3 1 時序錯誤偵測方法比較 13 表格 4 1 元件庫比較結果 43 表格 5 1 時序錯誤偵測及更正電路比較表 52 表格 5 2 各種時序錯誤及更正電路的FOM比較 53 表格 5 3 ISCAS89基準時序電路集檔案 54 表格 5 4 各個製程下的變異嚴重程度[32] 63 表格 5 5 ERFF及TG-MSFF在s349的蒙地卡羅比較 66 表格 5 6 ERFF及TG-MSFF在s386的蒙地卡羅比較 66 表格 5 7 s1196蒙地卡羅後比較表 67 表格 6 1 Leon3電晶體數量比較 73 表格 6 2 各種時序錯誤偵測及更正電路架構於Leon3中模擬數據 76 表格 6 3 於操作電壓0.3V下Leon3的模擬結果 82 表格 6 4 於Leon3中0.3v下蒙地卡羅前後的結果 83 | |
dc.language.iso | zh-TW | |
dc.title | 適用於寬廣操作電壓下容忍製程變異處理器之可容錯正反器與標準元件庫設計 | zh_TW |
dc.title | Error Resilient Flip-Flop and Standard Cell Library Design for Wide-operating-range Variation Tolerant Processors | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),蔡佩芸(Pei-Yun Tsai) | |
dc.subject.keyword | 低電壓元件庫,動態電壓頻率調整,時序錯誤偵測及更正,寬廣電壓操作處理器,低功耗電路設計, | zh_TW |
dc.subject.keyword | Low Voltage Cell Library,Dynamic Voltage Frequency Scaling,Timing Error Detection and Correction,Wide-Operating-Range Processor,Low Power Circuit Design, | en |
dc.relation.page | 92 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2013-12-03 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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