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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58769
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor胡振國(Jenn-Gwo Hwu)
dc.contributor.authorYu-Ching Liaoen
dc.contributor.author廖禹晴zh_TW
dc.date.accessioned2021-06-16T08:30:02Z-
dc.date.available2015-03-18
dc.date.copyright2014-03-18
dc.date.issued2013
dc.date.submitted2014-01-03
dc.identifier.citation[1] R. K. Cavin, “Science and Engineering Beyond Moore’s Law”, Proceeding of IEEE, vol. 100, issue: Special Centennial Issue, pp. 1720–1749, May 2012.
[2] W. Rhynes, “Keynote: ‘Less of Moore’,” TECHCON, Austin, TX, September 14,2009.
[3] C. W. Lee, “A Comprehensive Quantum-Mechanical Model for C-V and I-V Characteristics in Ultrathin MOS Structure and Experimental Verification”, M.S. thesis Dept. Elect. Eng, Nat. Taiwan Univ.,Taipei, Taiwan, R.O.C.,2013.
[4] P. F. Schmidt and W. Michel, “Anodic Formation of Oxide Films on Silicon”, Journal of the Electrochemical Society, vol. 104, p.230, 1957
[5] V. Parkhutik, “New Effects in the Kinetics of the Electrochemical Oxidation of Silicon”, Electrochimica Acta, vol. 45, pp.3249-3254, 2000
[6] M. Grecea, C. Rotaru, N. Nastase, and G. Craciun, “Physical Properties of SiO2 Thin Films Obtained by Anodic Oxidation”, Journal of Molecular Structure, pp.607-610, 1999
[7] S. K. Ghanghi, VLSI Fabrication Principles, 2nd ed., Wiley-Intersciencs, pp.487-495, 1994
[8] C. C. Ting,Y. H. Shih, J. G. Hwu, “Ultra Low Leakage Characteristics of Ultra-thin Gate Oxides (~3nm) Prepared by Anodization Followed by High Temperature Annealing”, IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 179–181,
2002.
[9] M. Sze, “Physics of Semiconductor Devices”, New York: Wiley, 1981
[10] K. Yang, Y. C. King, and C. Hu, “Quantum effect in oxide thickness determination from capacitance measurement,” VLSI Symp. Tech. Dig., pp. 77–78, 1999.
[11] R. Rios and N. D. Arora, “Determination of ultra-thin gate oxide thicknesses for CMOS structures using quantum effects,” in IEDM Tech. Dig., 1994, pp. 613–616.
[12] S.-H. Lo, D. A. Buchanan, and Y. Taur, “Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides,” IBM J. Res. Develop., vol. 43, no. 3, pp. 327–337, May 1999
[13] K. Yang, C. Hu, “MOS Capacitance Measurements for High-Leakage Thin Dielectrics”, IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1500-1501, July 1999.
[14] Berkeley Device Group. [Online], Available:
www-device.eecs.berkeley.edu/qmcv
[15] E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology (Wiley, New York, 1982) p.375
[16] A. Rusu and C. Bulucea, “Deep-depletion breakdown voltage of silicon-dioxide/silicon MOS capacitors,” IEEE Trans. Electron Devices, vol. ED-26, no. 3, pp. 201–205, March 1979.
[17]J. Y. Cheng, “Characterization of Edge Fringing Effect on the – Responses From Depletion to Deep Depletion of MOS(p) Capacitors With Ultrathin Oxide and High- Dielectric”, IEEE Trans. Electron Devices, vol. 49, no. 3, pp.565-572, March 2012
[18] K. M. Chen, “Area dependent deep depletion behavior in the capacitance-voltage characteristics of metal-oxide-semiconductor structures with ultra-thin oxides”,
J.Appl. Phys., vol.110, issue 11, pp. 114104 - 114104-4, December 2011
[19] J. Y. Cheng, C. T. Huang, and J. G. Hwu, “Comprehensive study on the deep depletion capacitance–voltage behavior for metal–oxide–semiconductor capacitor with ultrathin oxides,” J. Appl. Phys., vol. 106, no. 7, pp. 074507-1–074507-7, October 2009.
[20] R. Tsu, L. Esaki, “Tunneling in a Finite Superlattice”, Appl. Phys.Lett., vol. 22,no.11, pp.562, March 1973
[21] T. Y. Chen, “Two states phenomenon in the current behavior of metal-oxide-semiconductor capacitor structure with ultra-thin SiO2”, Appl. Phys.Lett., vol.101, no.7, pp.072506, August 2012
[22] C. H. Chen, K. C. Chuang, J. G. Hwu, “Characterization of Inversion Tunneling Current Saturation Behavior for MOS (p) Capacitors with Ultrathin Oxides and High-k Dielectrics”, IEEE Trans. Electron Devices, vol. 56, no. 6, pp.1262-1268,June 2009
[23] M. Y. Doghish, “A comprehensive analytical model for
metal-insulator-semiconductor (MIS) devices”, IEEE Trans. Electron Devices, vol. 39, no. 12, pp.2771-2780, December 1992
[24] M. Ershov, H. C. Liu, L. Li, M. Buchanan, “Negative Capacitance Effect in Semiconductor Devices”, IEEE Trans. Electron Devices, vol. 45, no. 10, pp.2196-2206, October 1998
[25] S.J. Chang, “Negative Capacitance Effect in Semiconductor Devices”, IEEE Trans. Electron Devices, vol. 58, no. 3, pp.684-690, March 2011
[26] P. Lundgren, M. O. Andersson, “Post-metallization annealing of metal-tunnel oxide-silicon diodes”, J. Appl. Phys., vol. 74, no. 7, pp. 4780-4782, October 1993.
[27] J. Campi, Y. Shi, Y. Luo, F. Yan and J.H. Zhao, “Study of Interface Density and Effective Oxide Charge in Post-Metallization Annealed SiO2/SiC Structures”, IEEE
Trans. Electron Devices, vol. 46, no. 3, pp.511-519, March 1999
[28] K. Takeuchi, T. Hiramoto, A. Nishida, “Random Fluctuations in Scaled MOS Devices”, Simulation of Semiconductor Processes and Devices, p.1-7, 2009.
[29] M. Motoyoshi, “Through-silicon Via”, Proceedings of IEEE, vol. 97, no. 1, pp.43-48, January 2009
[30] K. S. A. Butcher, T. L. Tansley, and D. Alexiev, “An instrumental solution to the phenomenon of negative capacitances in semiconductors,” Solid-State Electron., vol.
39, pp. 333–336, 1996.
[31] X. L. Huang et al., “Thermally induced capacitance and electric field domains in GaAs/AlO3GaO7As quantum well infrared photodetectors,” Solid-State Electron., vol.
41, pp. 845–850, 1997.
[32] A. K. Jonscher and M. N. Robinson, “Dielectric spectroscopy of silicon barrier devices,” Solid-State Electron., vol. 31, pp. 1277–1288, 1988.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58769-
dc.description.abstract本篇論文主要藉由深空乏現象來討論p 型基板與n 型矽基板超薄閘極氧化層
金氧半結構的不均勻效應。首先,主要應用李建緯學長的超薄氧化層金氧半電容
模型來解釋p 型與n 型矽基板金氧半電容本質上的差異,其中最主要的議題是對於p 型矽基板的金氧半電容而言,金屬和矽基板間的蕭基位障是不能被忽略的,但對於n 型基板的金氧半電容而言,蕭基位障的影響較小。此外,邊際電場效應會使得p 型基板的金氧半電容具有邊緣相關的電流特性,而n 型基板的金氧半電容的電流則是與面積相關;在第二部分有電流及電容對電壓的作圖來驗證此模型。n 型基板比起p 型基板的金氧半電容較快進入空乏區且具有較低的電容值,這個特性也與它本身漏流比較全面有關。為了再進一步討論及比較p 型與n 型基板的金氧半電容電荷的不均勻性,我們將元件照光來增加少數載子的數量。我們發現對於n 型基板的金氧半電容而言,在高頻下電容卻具有低頻的特性,這是由於n型基板內的少數載子具有較快的反應時間,儘管其本身漏流較p 型基板更大,而在p 型基板上則不會看到此低頻現象。在第三部分,我們使用後金屬退火與氧化層蝕刻來討論氧化層不均勻現象。我們發現到後金屬退火可以增加局部薄氧化層的面積且使氧化層的等效厚度減小,而對超薄閘極氧化層金氧半電容而言,甚至可能因為金屬穿透而使元件崩潰。對小面積的元件而言,因為不均勻面積占全部面積之比例較大,所以後金屬退火會使元件特性影響更為嚴重。同樣的,氧化層蝕刻也是對於小面積元件有較嚴重的影響。對大面積元件而言,因為它有較高比例會覆蓋到缺陷,所以它本身漏流較大且較早進入深空乏區域。此外,隨著閘極電壓增大,對於厚的氧化層元件而言,因為壓降主要在氧化層,所以厚的氧化層容易在量測過程中被破壞,而對於薄的氧化層元件而言,壓降主要在矽基板上,所以元件較不易被破壞。
zh_TW
dc.description.abstractIn this thesis, the non-uniformity effect of MOS (p) and MOS (n) capacitors with ultra-thin oxide were thoroughly investigated through deep depletion analysis. In the
first part, the theoretical model of ultra-thin oxide MOS capacitors proposed by Chien-Wei Lee was used to explain the abnormal behavior regarding MOS (p) and MOS (n) capacitors. The main issue is the Schottky barrier between metal and the
silicon substrate could not be ignored for MOS (p) capacitors but would be less pronounced for MOS (n) capacitors. In addition, the effect of fringing field would
further enhance the edge-dependent current conduction of MOS (p) capacitors. For MOS (n) capacitors, the current are area-dependent. In the second part, both I-V and
C-V measurements were performed to verify this model. It was found that MOS (n) capacitors enter into the deep depletion much quickly and show lower capacitance values than those of MOS (p) capacitors. These could also refer to the comprehensive leakage characteristics of MOS (n) capacitors. To further investigate the effect of charge non-uniformity in MOS (p) and MOS (n) capacitors, incandescent light was
applied to enhance the amount of minority carriers. For the MOS (n) capacitors, they reveal a low frequency effect at the 1MHz under light illumination due to a shorter
minority carrier response time despite the intrinsic leakier characteristic, but MOS (p) capacitors are not. In the third part, post-metallization annealing (PMA) and oxide etching were applied to discuss the oxide non-uniformity. It was found that PMA would extend the oxide local thinning area and reduce the effective thickness of the oxide layer. For ultra-thin oxide MOS (p) capacitors, it may further breakdown due to the metal spiking effect. For small-area devices, the effect of PMA would be much serious since the ratio of the non-uniform area to the entire area is higher. Similarly, oxide etching would cause serious oxide non-uniformity, particularly for small-area devices. For large-area devices, more defects are covered, the deep depletion occurs much quickly and are intrinsically leakier than small-or medium-area devices. Besides, it is noticed that thick oxide would encounter higher probability of breakdown during measurements since the voltage drop is mainly on oxide layer for thick-oxide MOS (p) capacitors, while mainly at silicon for thin oxide MOS (p) capacitors.
en
dc.description.provenanceMade available in DSpace on 2021-06-16T08:30:02Z (GMT). No. of bitstreams: 1
ntu-102-R00943164-1.pdf: 1303743 bytes, checksum: adc594641e03738ec39569ce2eee34ed (MD5)
Previous issue date: 2013
en
dc.description.tableofcontentsAbstract (Chinese)………………………………………………………………………………………I
Abstract (English)……………………………………………………………………………………II
Contents……………………………………………………………………………………………………………III
Figure Captions……………………………………………………………………………………………IV
Chapter 1 Introduction……………………………………………………………………………1
1-1 Motivation…………………………………………………………………………………………………1
1-2 Experimental Set-up and Measurement Systems……………………………………………………………………………………………………………………2
1-2-1 Anodization…………………………………………………………………………………………2
1-2-2 Experimental Process and Measurements……………………4
1-3 Determination of Silicon Oxide Thickness………………………………………………………………………………………………………………6
1-4 Deep Depletion Phenomenon…………………………………………………………8
1-5 Theoretical Model of the Ultra-thin Oxide MOS Capacitors……………………………………………………………………………………………………………10
Chapter 2 Basic Characteristics of Ultra-thin Oxide MOS Capacitors with p and n Substrates……………………………………………………………………………………………………………20
2-1 Introduction……………………………………………………………………………………………20
2-2 Capacitance-Voltage and Current-Voltage Curves Comparisons of MOS (p) and
MOS (n) Capacitors………………………………………………………………………………………20
2-2-1 C-V and I-V Curves Comparisons of Ultra-thin Oxide Small-Areas MOS
(p) and MOS (n) Capacitors…………………………………………………………………20
2-2-2 C-V and I-V Curves Comparisons of Ultra-thin Oxide Small-, Medium and Large-Areas MOS (p) and MOS (n) Capacitors……………………………………………………………………………………………………………27
2-3 p and n Substrate Deep Depletion Behaviors and Current-Voltage Curves
Comparisons under Dark and Illumination………………………………29
2-4 Summary…………………………………………………………………………………………………………34
III
Chapter 3 Ultra-thin Oxide Charge Non-uniformity Effect under Different Manufacturing Process……………………………………………………………………………………………………………………53
3-1 Introduction……………………………………………………………………………………………53
3-2 PMA Effect on Oxide Charge Non-uniformity……………………………………………………………………………………………………………53
3-2-1 PMA Effect for Small-Area MOS (p) Capacitors……………………………………………………………………………………………………………53
3-2-2 PMA Effect for Small-, Medium- and Large-Area MOS (p) Capacitors……………………………………………………………………………………………………………57
3-2-3 PMA Effect of Once and Twice PMA Treatments for Small-, Medium- and Large-Area MOS (p) Capacitors……………………………………………………………………………………………………………59
3-2-4 Summary of PMA effect………………………………………………………………60
3-3 Etching Effect on Oxide Charge Non-uniformity……………………………………………………………………………………………………………61
3-3-1 Etching Effect for Small-, Medium- and Large-Area MOS (p) Capacitors…………………………………………………………………………………………………61
3-3-2 Summary of the Oxide Etching Effect…………………………64
3-4 Thick Oxide Non-uniformity and Breakdown Characteristic ………………………………………………………………………………………………………………………………………65
3-4-1 Two-Peak C-V Curves Breakdown Characteristics of Non-uniform Oxide …………………………………………………………………………………………………65
3-4-2 The Vulnerability of Thick Oxide Breakdown after Illumination………………………………………………………………………………………………………67
3-4-3 Summary of the Thick Oxide Non-uniformity and Breakdown Characteristic………………………………………………………………………68
Chapter 4 Conclusions and Suggestions for Future Work……………………………………………………………………………………………………………………………85
4-1 Conclusions………………………………………………………………………………………………85
4-2 Suggestions for Future Work……………………………………………………88
References……………………………………………………………………………………………………………90
dc.language.isoen
dc.subject邊際電場zh_TW
dc.subject蕭基位障zh_TW
dc.subject金氧半電容zh_TW
dc.subject深空乏現象zh_TW
dc.subjectfringing fielden
dc.subjectSchottky barrieren
dc.subjectMOS capacitoren
dc.subjectdeep depletionen
dc.titlep 與n 基板超薄閘極氧化層金氧半結構元件之深空乏現象與氧化層不均勻現象探討zh_TW
dc.titleInvestigation of the Deep Depletion Behavior and
Oxide Charge Non-Uniformity Effect in MOS (p) and
MOS (n) Devices with Ultra-Thin Oxides
en
dc.typeThesis
dc.date.schoolyear102-1
dc.description.degree碩士
dc.contributor.oralexamcommittee吳肇欣(Chao-Hsin Wu),李峻霣(Jiun-Yun Li),鄭晃忠(Huang-Chung Cheng)
dc.subject.keyword深空乏現象,蕭基位障,邊際電場,金氧半電容,zh_TW
dc.subject.keyworddeep depletion,Schottky barrier,fringing field,MOS capacitor,en
dc.relation.page94
dc.rights.note有償授權
dc.date.accepted2014-01-03
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
顯示於系所單位:電子工程學研究所

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