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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58678完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李致毅(Jri Lee) | |
| dc.contributor.author | Guan-Sing Chen | en |
| dc.contributor.author | 陳冠行 | zh_TW |
| dc.date.accessioned | 2021-06-16T08:25:18Z | - |
| dc.date.available | 2019-03-18 | |
| dc.date.copyright | 2014-03-18 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-01-21 | |
| dc.identifier.citation | [1] IEEE P802.3ba 40Gb/s and 100Gb/s Ethernet Task Force [Online]. Available: http://www.ieee802.org/3/ba/
[2] Universal Serial Bus [Online]. Available: http://www.usb.org/ [3] Serial ATA [Online]. Available: http://www.sata-io.org/ [4] PCI-SIG [Online]. Available: http://www.pcisig.com/ [5] B. Razavi, Design of Integrated Circuits for Optical Communications. New York: McGRAW-HILL, 2002. [6] Chen, Ming-Shuan, and Chih-Kong Ken Yang. 'A low-power highly multiplexed parallel PRBS generator.' Custom Integrated Circuits Conference (CICC), 2012 IEEE. IEEE, 2012. [7] Roine, Per Torstein. 'An asynchronous PRBS error checker for testing high-speed self-clocked serial links.' Advanced Research in Asynchronous Circuits and Systems, 1998. Proceedings. 1998 Fourth International Symposium on. IEEE, 1998. [8] J. Lee, “A 20Gb/s Adaptive Equalizer in 0.13μm CMOS Technology,” ISSCC Dig. Tech. Papers, pp 273-282, Feb. 2006. [9] Jri Lee, 'A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology,' IEEE Journal of Solid-State Circuits, vol. 41, pp. 2058-2066, Sept. 2006 [10] Dalton, Declan, et al. 'A 12.5-Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback.' Solid-State Circuits, IEEE Journal of 40.12 (2005): 2713-2725. [11] Hanumolu, Pavan Kumar, Gu-Yeon Wei, and Un-Ku Moon. 'A wide-tracking range clock and data recovery circuit.' Solid-State Circuits, IEEE Journal of43.2 (2008): 425-439. [12] Jeon, Hyung-Joon, et al. 'A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy.' IEEE JOURNAL OF SOLID-STATE CIRCUITS 48.6 (2013). [13] Jri Lee and K. Wu, 'A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition, ' IEEE Journal of Solid-State Circuits, vol. 44, pp. 3590-3602, Dec. 2009. [14] Jri Lee and K. Wu, ' A 20Gb/s Full-Rate Linear CDR Circuit with Automatic Frequency Acquisition,' Digest of International Solid-State Circuits Conference, pp. 366-367, Feb. 2009 [15] J. C. Scheytt et al., “A 0.155, 0.622, and 2.488 Gb/s Automatic Bit Rate Selecting Clock and Data Recovery IC for Bit Rate Transparent SDH Systems,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 348-349, Feb. 1999. [16] Kocaman, Namik, et al. 'An 8.5–11.5 Gbps SONET transceiver with referenceless frequency acquisition.' Custom Integrated Circuits Conference (CICC), 2012 IEEE. IEEE, 2012. [17] J. Lee et al., “A 75-GHz Phase-locked Loop in 90-nm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, Jun. 2008. [18] J. Lee, “High-speed Circuit Designs for Transmitters in Broadband Data Links,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1004-1015, May 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58678 | - |
| dc.description.abstract | 在本文中，我們將會介紹三個使用CMOS製作的有線背板電路系統，包含了應用於測量錯誤率的有線接收器、偽隨機二進位序列產生器、寬頻(600Mb/s-4Gb/s)接收器、以及24Gb/s接收器。在這些有線背板電路系統中，都包含了幾種背板通訊有線接收器的主要電路──¬¬類比等化器、以及解多工器、時脈資料回復電路、錯誤偵測器。
在測量錯誤率的有線接收器中，包含了類比等化器、解多工器、錯誤偵測器。本系統可以用來測試27-1、215-1、223-1、231-1偽隨機二進位序列產生器。此外，電路內也同時可以產生這四種偽隨機二進位序列產生器。並可以執行自我測試的功能，本系統與偽隨機二進位序列產生器是一整合的晶片。同時可以產生四路偽隨機二進位序列產生器以及測試輸入資料的錯誤率。 在寬頻(600Mb/s-4Gb/s)接收器中，包含了類比等化器、時脈資料回復電路、解多工器，這個電路在1.2V的操作下，可以涵蓋600Mb/s到4Gb/s的這個頻段同時消耗360毫瓦。本接收器主要應用於大尺寸電視。 在24Gb/s接收器中，包含了類比等化器、時脈資料回復電路、解多工器，這個系統在1.2電壓操作下消耗350毫瓦。這接收器主要是應用在3G-SDI的資料處理上。 關鍵詞：類比等化器、時脈資料回復電路、偽隨機二進位序列、頻率偵測器、解多工器、錯誤率偵測器 | zh_TW |
| dc.description.abstract | In this thesis, three wireline backplane circuit systems will be demonstrated, including the bit error rate tester, the pattern generator, a 600Mb/s to 4Gb/s receiver and a 24Gb/s receiver. These wireline backplane circuit systems consist of some critical component – an analog equalizer, a clock and data recovery circuit (CDR), and a demultiplexer (DMUX).
The bit error rate tester includes an analog equalizer, DMUX, error detector. This system is used for test the four different pseudo random binary sequence: 27-1、215-1、223-1、231-1. Besides, the circuit also can generate these four different PRBS and built-in self-testing function is also included in this chip. This system and PRBS generator are integrated into one chip. This chip can generate four lanes PRBS and test input bit error rate at the same time. The wideband (600Mb/s-4Gb/s) receiver consists of an analog equalizer, a clock and data recovery circuit (CDR) and a demultiplexer (DMUX). The system consumes 360mW from a 1.2-V supply and covers the incoming data rate from 600Mb/s to 4Gb/s. This receiver is mainly applied for the 4K-2K high resolution TV. The 24Gb/s receiver consists of an analog equalizer, a clock and data recovery circuit (CDR) and a demultiplexer (DMUX). The system consumes 350mW from a 1.2-V supply. This receiver is mainly applied for the 3G-SDI application. Key words: Analog Equalizer, Clock and Data Recovery Circuit (CDR), Pseudo Random Binary Sequence, Demultiplexer (DMUX), Bit Error Rate Tester | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T08:25:18Z (GMT). No. of bitstreams: 1 ntu-103-R00943134-1.pdf: 3205149 bytes, checksum: 3398d9dee9ea86c1f94957f1f4f18f59 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 摘要 I
ABSTRACT II CONTENTS III LIST OF FIGURES V LIST OF TABLES VIII Chapter 1 Introduction 1 1.1 Motivation 2 1.2 Thesis Organization 2 Chapter 2 2G~10G BERT 3 2.1 Introduction 3 2.2 Transceiver Architecture 3 2.3 Pattern Generator Architecture 4 2.4 Error Detector Architecture 5 2.5 Digitally Controlled Equalizer 8 2.6 DEMUX Architecture 9 2.7 Serial Data Interconnection 10 2.7.1 CHIP to 8051 10 2.7.2 PC to 8051 12 2.8 Measurement Result 13 2.9 Performance Summary 16 Chapter 3 600M~4G Receiver 18 3.1 Introduction 18 3.2 Receiver Architecture 18 3.3 Adaptive Equalizer Architecture 19 3.4 CDR Architecture 20 3.4.1 Phase Detection 20 3.4.2 Frequency Lock Loop 21 3.5 Building Block 22 3.5.1 VCO 22 3.5.2 V/I Converter 23 3.5.3 Coarse Frequency Detector 24 3.6 Demultiplexer Architecture 25 3.7 ALN Architecture 28 3.8 Simulation Results 29 3.9 Measurement setup 32 3.10 Performance Summary 33 Chapter 4 24G Receiver 34 4.1 Introduction 34 4.2 Receiver Architecture 34 4.3 Adaptive Equalizer Architecture 35 4.4 CDR Architecture 36 4.4.1 Phase Detection 36 4.4.2 Frequency Acquisition 38 4.5 Building Block 40 4.5.1 VCO and Clock Buffer 41 4.5.2 Flip-flop 42 4.5.3 V/I Converters 43 4.6 Demultiplexer Architecture 44 4.7 Simulation Results 46 4.8 Measurement setup 48 4.9 Performance Summary 49 Chapter 5 Conclusion 51 Bibliography 52 | |
| dc.language.iso | zh-TW | |
| dc.subject | 類比等化器 | zh_TW |
| dc.subject | 時脈資料回復電路 | zh_TW |
| dc.subject | 頻率偵測器 | zh_TW |
| dc.subject | 解多工器 | zh_TW |
| dc.subject | 錯誤率偵測器 | zh_TW |
| dc.subject | Pseudo Random Binary Sequence | en |
| dc.subject | Analog Equalizer | en |
| dc.subject | Clock and Data Recovery Circuit | en |
| dc.subject | Demultiplexer | en |
| dc.subject | Bit Error Rate Tester | en |
| dc.title | 三種不同應用的有線接收器 | zh_TW |
| dc.title | Three different receiver architectures for specific applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 謝秉璇(Ping-Hsuan Hsieh),林宗賢(Tsung-Hsien Lin) | |
| dc.subject.keyword | 類比等化器,時脈資料回復電路,頻率偵測器,解多工器,錯誤率偵測器, | zh_TW |
| dc.subject.keyword | Analog Equalizer,Clock and Data Recovery Circuit,Pseudo Random Binary Sequence,Demultiplexer,Bit Error Rate Tester, | en |
| dc.relation.page | 53 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-01-22 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-103-1.pdf 未授權公開取用 | 3.13 MB | Adobe PDF |
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